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楼主 |
发表于 2010-3-10 19:31:51
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回复【1楼】yuhang
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cordic算法,大致编译一下,占用资源吓人,一下子几百个LE就没了.
唉,先整一个简单的将就够用,可以22.5度/BIT移相.闲话少说,先帖代码,兑现承诺.
module rclk (bclk,clr,in,rclk);
input bclk,clr;
input[3:0] in;
output rclk;
//wire clock;
reg rclk_cnt;
reg[3:0] cout;
always @(posedge bclk or negedge clr)
begin
if(!clr)
begin
cout <= in;
rclk_cnt <= 1;
end
// else if (preset == 1)
// cout <=in;
else
begin
if(cout == 0)
begin
// cout <= in;
rclk_cnt <=0;
end
else
begin
cout <=cout-1;
rclk_cnt<=1;
end
end
end
clk_div16 s1 (bclk,clr,rclk_cnt,rclk);
//assign rclk = clock;
endmodule
module clk_div16 (clk_in,clr,enable,clk_out);
input clk_in,clr,enable;
output clk_out;
reg clk_out;
reg[2:0] cnt;
always @(posedge clk_in or negedge clr or posedge enable)
begin
if (!clr)
clk_out <= 0;
else if (enable)
begin
cnt <=7;
clk_out <= 1;
end
else
begin
if (cnt == 0)
begin
cnt <= 7;
clk_out <= ~clk_out;
end
else
begin
cnt <= cnt-1;
clk_out <= clk_out;
end
end
end
endmodule |
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发表于 2010-2-9 16:16:39
