|
我写了一个PWM发生程序,需要单片机给FPGA发送占空比,可是怎么也不对,用的是51单片机的P0,P2口
PWM 的verilog 代码:
`define pwm_width_addr 16'hff00
`define pwm_period_addr 16'hff01
`define no_rw 2'h0
`define rw_pwmwidth 2'h1
`define rw_pwmperiod 2'h2
module pwm(mcu_ad,mcu_a,ale,wr,rd,pwm,clk);
inout [7:0] mcu_ad;
input [7:0] mcu_a;
input ale;
input wr;
input rd;
output [5:0] pwm;
input clk;
reg [7:0] mcu_ad_reg;
reg [5:0] pwm_reg;
reg [7:0] count;
reg [7:0] width_count;
reg [7:0] period_count;
reg [1:0] addr_sel;
initial
begin
period_count=8'b11111111;
width_count=8'b00000000;
end
always @ (negedge ale)
begin
if({mcu_a,mcu_ad}== `pwm_width_addr)
begin
addr_sel = `rw_pwmwidth;
end
else if({mcu_a,mcu_ad}==`pwm_period_addr)
begin
addr_sel=`rw_pwmperiod;
end
else
addr_sel= `no_rw;
end
always @ (posedge wr)
begin
if(addr_sel== `rw_pwmwidth)
width_count = mcu_ad;
else if(addr_sel==`rw_pwmperiod)
period_count = mcu_ad;
end
always @(negedge rd)
begin
if(addr_sel== `rw_pwmwidth)
mcu_ad_reg=width_count;
else if (addr_sel==`rw_pwmperiod)
mcu_ad_reg=period_count;
end
always @ (posedge clk)
begin
if(count>=period_count-1)
count<=0;
else
count<=count+1;
end
always @ (posedge clk)
begin
if(count<width_count)
pwm_reg=6'b111111;
else
pwm_reg=6'b000000;
end
assign mcu_ad=((rd==1'b1)||(addr_sel==`no_rw))?8'hz:mcu_ad_reg;
assign pwm=pwm_reg;
endmodule
C51 代码:
#include"reg51.h"
#include"address.h"
#include"intrins.h"
#define uint unsigned int
#define uchar unsigned char
void wr_pwm(unsigned int ADDR, unsigned char DATA)
{
*((unsigned char xdata *)ADDR)=DATA;
}
unsigned char rd_pwm(unsigned int ADDR)
{
return *((unsigned char xdata *)ADDR);
}
void delay_10us(uchar n)
{
do
{
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
}while(--n);
}
void delay_ms(uint n)
{
do
{
delay_10us(131);
}while(--n);
}
void main()
{
wr_pwm(pwm_period_addr,0xff);
wr_pwm(pwm_width_addr,0x00);
delay_ms(10);
while (1)
{
pwm_width=pwm_width+1;
wr_pwm(pwm_width_addr,pwm_width);
if(pwm_width==0xff)
pwm_width=0;
delay_ms(100);
}
}
请高手指点一下,谢谢, |
阿莫论坛20周年了!感谢大家的支持与爱护!!
该献的血还是要献的。你不献他不献。难道让我去献? --- 出自坛友:lovejp1981
|