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我现在用单片机和CPLD以总线的方式连接，
我的想法是,数据总线传输数据，然后到CPLD里面处理，处理后以不同的通讯方式传输出去，如:UART.IIC,SPI等方式！
但是我把所有的IO分组，每组4个IO口，这4个IO口可以用来做UART,SPI,IIC和4个IO口,这个可以通过2根控制总线来选择!
我所有组的通讯方式可以变化，也就是说,如果我这个组的想做UART,我下个时刻我想做IIC,
我现在用的VHDL语言来实现，但是我如果用case语句来做的话，总是提示有警告！不知道怎么解决！我贴出代码！希望能帮我解决下！
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MODULE is
------------------------------------------
port (
MODULE_RST: in std_logic;
MODULE_ADDRIN: in std_logic_vector( 1 downto 0 );
MODULE_OUT: out std_logic_vector( 3 downto 0 );
MODULE_IN: in std_logic_vector( 3 downto 0 )
);
------------------------------------------
end MODULE;
architecture Behavioral of MODULE is
------------------------------------------
component BUFGP
port ( I: in std_logic; O: out std_logic );
end component;
------------------------------------------
------------------------------------------
signal MoudleOUT: std_logic;
signal MoudleIN: std_logic;
------------------------------------------
begin
MODULE_ADDR_SEL:
process ( MODULE_RST,MODULE_ADDRIN )
begin
if ( MODULE_RST = '0' ) then
case MODULE_ADDRIN is
when "00" =>
MoudleIN <= MODULE_IN(0);
MODULE_OUT(0) <= MoudleOUT ;
when "01" =>
MoudleIN <= MODULE_IN(1);
MODULE_OUT(1) <= MoudleOUT ;
when "10" =>
MoudleIN <= MODULE_IN(2);
MODULE_OUT(2) <= MoudleOUT ;
when "11" =>
MoudleIN <= MODULE_IN(3);
MODULE_OUT(3) <= MoudleOUT ;
when others =>
null;
end case;
end if;
end process MODULE_ADDR_SEL;
end Behavioral;
但是总是有警告，大概意思就是说有latch什么的！
WARNING:Xst:819 - "G:/MG/MGLM/code/CPLD/PJ092703T/src/MODULE.vhd" line 53: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
WARNING:Xst:653 - Signal <MoudleOUT> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <MoudleIN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_3> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_2> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_1> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_0> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Cpld:1006 - Design 'MODULE' has no inputs.
WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F =
WARNING:Cpld:310 - Cannot apply TIMESPEC AUTO_TS_P2P =
WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F =
WARNING:Cpld:310 - Cannot apply TIMESPEC AUTO_TS_F2P =
希望能帮我解决下！ |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2009-7-5 08:49:41
楼主