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VGA程序更新-Verilog版本显示四种模式
点击此处下载 ourdev_421275.rar(文件大小:127K) (原文件名:EP2C5Q208_vga.rar)
说明：对应本站的EP2C5Q208开发板和接口板直接下载即可运行，其余开发板可以自行重新建立工程文件，
不是很麻烦，本站有教如何创建工程，只需要把里面的v文件拷贝，重新建立即可
实验过程：下载代码之后，直接可以驱动VGA显示，通过接口板上的薄码开关8和7 可以控制四种模式
横条 竖条 棋盘格A 棋盘格B
例程参考周立功的试验，这里表示感谢！
关于VGA的资料可以参考以下网站，同时本站近期也将推出我们的视频驱动教程文档，敬请关注
http://www.tinyvga.com/vga-timing/640x480@60Hz
http://www.pyroelectro.com/tutorials/vhdl_vga/theory.html
(原文件名:1.jpg)
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(原文件名:3.jpg)
(原文件名:4.jpg)
(原文件名:5.jpg)
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附源程序如下啊：
module vga(
clock,
switch,
disp_RGB,
hsync,
vsync
);
input clock; //系统输入时钟 50MHz
input [1:0]switch;
output [2:0]disp_RGB; //VGA数据输出
output hsync; //VGA行同步信号
output vsync; //VGA场同步信号
reg [9:0] hcount; //VGA行扫描计数器
reg [9:0] vcount; //VGA场扫描计数器
reg [2:0] data;
reg [2:0] h_dat;
reg [2:0] v_dat;
//reg [9:0] timer;
reg flag;
wire hcount_ov;
wire vcount_ov;
wire dat_act;
wire hsync;
wire vsync;
reg vga_clk;
//VGA行、场扫描时序参数表
parameter hsync_end = 10'd95,
hdat_begin = 10'd143,
hdat_end = 10'd783,
hpixel_end = 10'd799,
vsync_end = 10'd1,
vdat_begin = 10'd34,
vdat_end = 10'd514,
vline_end = 10'd524;
always @(posedge clock)
begin
vga_clk = ~vga_clk;
end
//************************VGA驱动部分*******************************
//行扫描
always @(posedge vga_clk)
begin
if (hcount_ov)
hcount <= 10'd0;
else
hcount <= hcount + 10'd1;
end
assign hcount_ov = (hcount == hpixel_end);
//场扫描
always @(posedge vga_clk)
begin
if (hcount_ov)
begin
if (vcount_ov)
vcount <= 10'd0;
else
vcount <= vcount + 10'd1;
end
end
assign vcount_ov = (vcount == vline_end);
//数据、同步信号输
assign dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end))
&& ((vcount >= vdat_begin) && (vcount < vdat_end));
assign hsync = (hcount > hsync_end);
assign vsync = (vcount > vsync_end);
assign disp_RGB = (dat_act) ? data : 3'h00;
//************************显示数据处理部分*******************************
//图片显示延时计数器
/*always @(posedge vga_clk)
begin
flag <= vcount_ov;
if(vcount_ov && ~flag)
timer <= timer + 1'b1;
end
*/
always @(posedge vga_clk)
begin
case(switch[1:0])
2'd0: data <= h_dat; //选择横彩条
2'd1: data <= v_dat; //选择竖彩条
2'd2: data <= (v_dat ^ h_dat); //产生棋盘格
2'd3: data <= (v_dat ~^ h_dat); //产生棋盘格
endcase
end
always @(posedge vga_clk) //产生竖彩条
begin
if(hcount < 223)
v_dat <= 3'h7; //白
else if(hcount < 303)
v_dat <= 3'h6; //黄
else if(hcount < 383)
v_dat <= 3'h5; //青
else if(hcount < 463)
v_dat <= 3'h4; //绿
else if(hcount < 543)
v_dat <= 3'h3; //紫
else if(hcount < 623)
v_dat <= 3'h2; //红
else if(hcount < 703)
v_dat <= 3'h1; //蓝
else
v_dat <= 3'h0; //黑
end
always @(posedge vga_clk) //产生横彩条
begin
if(vcount < 94)
h_dat <= 3'h7; //白
else if(vcount < 154)
h_dat <= 3'h6; //黄
else if(vcount < 214)
h_dat <= 3'h5; //青
else if(vcount < 274)
h_dat <= 3'h4; //绿
else if(vcount < 334)
h_dat <= 3'h3; //紫
else if(vcount < 394)
h_dat <= 3'h2; //红
else if(vcount < 454)
h_dat <= 3'h1; //蓝
else
h_dat <= 3'h0; //黑
end
endmodule |
阿莫论坛20周年了！感谢大家的支持与爱护！！
曾经有一段真挚的爱情摆在我的面前，我没有珍惜，现在想起来，还好我没有珍惜……
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发表于 2009-2-21 15:43:25
