CPU: AMCC PowerPC 460EX Rev. A at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
Security/Kasumi support
Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
Internal PCI arbiter disabled
32 kB I-Cache 32 kB D-Cache
Board: XXXX PPC460EX Evaluation Board, 2*PCIe, Rev. 13
I2C: ready
DRAM: 512 MB (ECC not enabled, 400 MHz, CL3)
FLASH: 64 MB
NAND: 128 MiB
PCI: Bus Dev VenId DevId Class Int
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: link is not up.
PCIE1: initialization as root-complex failed
DTT: 1 is 23 C
DTT: 2 is 58 C
Net: ppc_4xx_eth0, ppc_4xx_eth1
Type run flash_nfs to mount root filesystem over NFS
CPU: AMCC PPC460EX Canyonlands. Processor #0.
Memory Size: 0x20000000. BSP version 1.2/3.
WDB Comm Type: WDB_COMM_END
WDB: Ready.
-> pciConfigTopoShow
[0,0,0] type=OTHER DEVICE
status=0xffff ( CAP 66MHZ UDF FBTB DATA_PARITY_ERR DEVSEL=3 TGT_ABORT_GEN TGT_ABORT_RCV MSTR_ABORT_RCV ASSERT_SERR PARITY_ERR )
command=0xffff ( IO_ENABLE MEM_ENABLE MASTER_ENABLE MON_ENABLE WI_ENABLE SNOOP_ENABLE PERR_ENABLE WC_ENABLE SERR_ENABLE FBTB_ENABLE )
[0,6,0] type=OTHER DEVICE
status=0x02b0 ( CAP 66MHZ FBTB DEVSEL=1 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
bar0 in 32-bit mem space @ 0x50000000
bar1 in I/O space @ 0x00800000
bar2 in 32-bit mem space @ 0x50010000
bar3 in 32-bit mem space @ 0x50100000
value = 0 = 0x0
-> pciDeviceShow 0
Scanning function 0 of each PCI device on bus 0
Using configuration mechanism 0
bus device function vendorID deviceID class
00000000 00000006 00000000 000010b5 00009656 00ff0000
value = 0 = 0x0
-> pciHeaderShow 0,6,0
vendor ID = 0x10b5
device ID = 0x9656
command register = 0x0007
status register = 0x02b0
revision ID = 0xba
class code = 0xff
sub class code = 0x00
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0x50000000
base address 1 = 0x00800001
base address 2 = 0x50010000
base address 3 = 0x50100000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x10b5
sub system ID = 0x9656
expansion ROM base address = 0x00000000
interrupt line = 0x20
interrupt pin = 0x01
min Grant = 0x40
max Latency = 0x80
value = 0 = 0x0
->
PCI: Bus Dev VenId DevId Class Int
00 06 10b5 9656 ff00 09
PCIE0: successfully set as root-complex
02 00 10b5 8112 0604 00
PCIE1: link is not up.
PCIE1: initialization as root-complex failed
PCI: Bus Dev VenId DevId Class Int
00 06 10b5 9656 ff00 09
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: successfully set as root-complex
02 00 10b5 8112 0604 00
-> sysPciConfigEnable(0)
value = 168464 = 0x29210 = pciAutoRegConfig + 0xfe4
-> pciConfigTopoShow
[0,0,0] type=P2P BRIDGE to [1,0,0]
base/limit:
mem= 0x70000000/0x6fffffff
preMem=0x0000000060000000/0x000000005fffffff
I/O= 0x80000000/0x7fffffff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[0,0,0] type=P2P BRIDGE to [1,0,0]
base/limit:
mem= 0x70000000/0x6fffffff
preMem=0x0000000060000000/0x000000005fffffff
I/O= 0x80000000/0x7fffffff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
value = 0 = 0x0
-> pciDeviceShow 0
Scanning function 0 of each PCI device on bus 0
Using configuration mechanism 0
bus device function vendorID deviceID class
00000000 00000000 00000000 000010e8 00000000 00060400
value = 0 = 0x0
-> sysPciConfigEnable(1)
value = 168464 = 0x29210 = pciAutoRegConfig + 0xfe4
-> pciConfigTopoShow
[0,0,0] type=P2P BRIDGE to [1,0,0]
base/limit:
mem= 0xb0000000/0xafffffff
preMem=0x00000000a0000000/0x000000009fffffff
I/O= 0xc0000000/0xbfffffff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[0,0,0] type=P2P BRIDGE to [1,0,0]
base/limit:
mem= 0xb0000000/0xafffffff
preMem=0x00000000a0000000/0x000000009fffffff
I/O= 0xc0000000/0xbfffffff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[1,0,0] type=P2P BRIDGE to [2,0,0]
base/limit:
mem= 0xb0000000/0xafffffff
preMem=0xa0000000/0x9fffffff
I/O= 0x0000/0xffff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
value = 0 = 0x0
-> pciDeviceShow 0
Scanning function 0 of each PCI device on bus 0
Using configuration mechanism 0
bus device function vendorID deviceID class
00000000 00000000 00000000 000010e8 00000000 00060400
value = 0 = 0x0
-> pciDeviceShow 1
Scanning function 0 of each PCI device on bus 1
Using configuration mechanism 0
bus device function vendorID deviceID class
00000001 00000000 00000000 000010b5 00008112 00060400
value = 0 = 0x0
-> pciHeaderShow 1,0,0
vendor ID = 0x10b5
device ID = 0x8112
command register = 0x0007
status register = 0x0010
revision ID = 0xaa
class code = 0x06
sub class code = 0x04
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x01
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
primary bus number = 0x01
secondary bus number = 0x02
subordinate bus number = 0x02
secondary latency timer = 0x00
IO base = 0x00
IO limit = 0xf0
secondary status = 0x2220
memory base = 0xb000
memory limit = 0xaff0
prefetch memory base = 0xa000
prefetch memory limit = 0x9ff0
prefetch memory base upper = 0x00000000
prefetch memory limit upper = 0x00000000
IO base upper 16 bits = 0x0000
IO limit upper 16 bits = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x70
interrupt pin = 0x01
bridge control = 0x0000
value = 0 = 0x0
-> sysPciConfigEnable(1)
value = 168464 = 0x29210 = pciAutoRegConfig + 0xfe4
-> pciConfigTopoShow
[0,0,0] type=P2P BRIDGE to [1,0,0]
base/limit:
mem= 0xb0000000/0xb01fffff
preMem=0x00000000a0000000/0x000000009fffffff
I/O= 0xc0000000/0xc0000fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[0,0,0] type=P2P BRIDGE to [1,0,0]
base/limit:
mem= 0xb0000000/0xb01fffff
preMem=0x00000000a0000000/0x000000009fffffff
I/O= 0xc0000000/0xc0000fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[1,0,0] type=P2P BRIDGE to [2,0,0]
base/limit:
mem= 0xb0000000/0xb01fffff
preMem=0xa0000000/0x9fffffff
I/O= 0x0000/0x0fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[2,0,0] type=OTHER DEVICE
status=0x02b0 ( CAP 66MHZ FBTB DEVSEL=1 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
bar0 in 32-bit mem space @ 0xb0000000
bar1 in I/O space @ 0xc0000000
bar2 in 32-bit mem space @ 0xb0010000
bar3 in 32-bit mem space @ 0xb0100000
value = 0 = 0x0
-> pciDeviceShow 0
Scanning function 0 of each PCI device on bus 0
Using configuration mechanism 0
bus device function vendorID deviceID class
00000000 00000000 00000000 000010e8 00000000 00060400
value = 0 = 0x0
-> pciDeviceShow 1
Scanning function 0 of each PCI device on bus 1
Using configuration mechanism 0
bus device function vendorID deviceID class
00000001 00000000 00000000 000010b5 00008112 00060400
value = 0 = 0x0
-> pciDeviceShow 2
Scanning function 0 of each PCI device on bus 2
Using configuration mechanism 0
bus device function vendorID deviceID class
00000002 00000000 00000000 000010b5 00009656 00ff0000
value = 0 = 0x0
-> pciHeaderShow 1,0,0
vendor ID = 0x10b5
device ID = 0x8112
command register = 0x0007
status register = 0x0010
revision ID = 0xaa
class code = 0x06
sub class code = 0x04
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x01
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
primary bus number = 0x01
secondary bus number = 0x02
subordinate bus number = 0x02
secondary latency timer = 0x00
IO base = 0x00
IO limit = 0x00
secondary status = 0x2220
memory base = 0xb000
memory limit = 0xb010
prefetch memory base = 0xa000
prefetch memory limit = 0x9ff0
prefetch memory base upper = 0x00000000
prefetch memory limit upper = 0x00000000
IO base upper 16 bits = 0x0000
IO limit upper 16 bits = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x70
interrupt pin = 0x01
bridge control = 0x0000
value = 0 = 0x0
-> pciHeaderShow 2,0,0
vendor ID = 0x10b5
device ID = 0x9656
command register = 0x0007
status register = 0x02b0
revision ID = 0xba
class code = 0xff
sub class code = 0x00
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0xb0000000
base address 1 = 0xc0000001
base address 2 = 0xb0010000
base address 3 = 0xb0100000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x10b5
sub system ID = 0x9656
expansion ROM base address = 0x00000000
interrupt line = 0x70
interrupt pin = 0x01
min Grant = 0x40
max Latency = 0x80
value = 0 = 0x0
-> d 0xb0000000,64,4
b0000000: 0000ffff 01000000 ff002301 00053000 *..........#...0.*
b0000010: 00000000 00000000 4f01034a 00000000 *........O..J....*
b0000020: 00000000 00000000 00000000 00000000 *................*
b0000030: 00000000 08000000 00000000 00000000 *................*
b0000040: 00000000 00000000 00000000 00000000 *................*
b0000050: 00000000 00000000 00000000 00000000 *................*
b0000060: 00000000 00000000 0001010f 7e760d10 *............~v..*
b0000070: b5105696 ba000000 00000000 00000000 *..V.............*
b0000080: 43000000 00000000 00000000 00000000 *C...............*
b0000090: 00000000 43000000 00000000 00000000 *....C...........*
b00000a0: 00000000 00000000 10100000 ff002301 *..............#.*
b00000b0: 00000000 00000000 00000000 00000000 *................*
b00000c0: 02000000 00000000 00000000 00000000 *................*
b00000d0: 00000000 00000000 00000000 00000000 *................*
b00000e0: 00000000 00000000 50000000 00000000 *........P.......*
b00000f0: 0000f0ff 01001000 c3010000 00000000 *................*
value = 21 = 0x15
-> d 0xb0010000
b0010000: 0000ffff 0c00ffff 0c00ffff ff00ffff *................*
b0010010: ff1fffff 0000ffff 0000ffff 0000ffff *................*
b0010020: 3e00ffff 3e00ffff 0600ffff 1b00ffff *>...>...........*
b0010030: 0300ffff 880effff 0040ffff 0004ffff *.........@......*
b0010040: aa00ffff ffffffff 0000ffff 0000ffff *................*
b0010050: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b0010060: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b0010070: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b0010080: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b0010090: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b00100a0: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b00100b0: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b00100c0: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b00100d0: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b00100e0: 0000ffff 0000ffff 0000ffff 0000ffff *................*
b00100f0: 0000ffff 0000ffff 0000ffff 0000ffff *................*
value = 21 = 0x15
->
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~zhang
PCI: Bus Dev VenId DevId Class Int
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: successfully set as root-complex
02 00 10ee 0007 1180 ff
=> pci header 2.0.0
vendor ID = 0x10ee
device ID = 0x0007
command register = 0x0006
status register = 0x0010
revision ID = 0x00
class code = 0x11 (DSP)
sub class code = 0x80
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0xb8000000
base address 1 = 0xb8200000
base address 2 = 0xbc000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x10ee
sub system ID = 0x0007
expansion ROM base address = 0x00000000
interrupt line = 0xff
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~gan
PCI: Bus Dev VenId DevId Class Int
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: successfully set as root-complex
02 00 10ee 0007 0580 ff
=> pci header 2.0.0
vendor ID = 0x10ee
device ID = 0x0007
command register = 0x0006
status register = 0x0010
revision ID = 0x02
class code = 0x05 (Memory controller)
sub class code = 0x80
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0xb800000c
base address 1 = 0x00000000
base address 2 = 0x00000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x10ee
sub system ID = 0x0007
expansion ROM base address = 0x00000000
interrupt line = 0xff
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~作者: shixm.zh 时间: 2009-12-17 11:52
冒昧的问一下dspsharc 你在哪个城市?作者: powu 时间: 2009-12-17 12:53
呵呵,我这也有BDI2000,交流一下ROM吧作者: shixm.zh 时间: 2009-12-17 13:16
42楼楼主:你的软件是针对什么处理器的?作者: stdio 时间: 2009-12-17 13:17
shixm.zh:不是FPGA就是PPC,净整些高难的东东,大公司出来的吧?作者: shixm.zh 时间: 2009-12-17 13:21
呵呵,没有啦,从没有在大公司干过,不过经常和大公司的人打交道,还有更难的东西呢,16核的网络处理器,不知道有没有人关心过?已经关注3年多了,一直想搞。作者: XU_MAJIA 时间: 2009-12-17 14:53
v作者: yoko 时间: 2009-12-17 15:16
请问楼主用什么软件画的板子?作者: shixm.zh 时间: 2009-12-17 15:44
请问楼主用什么软件画的板子?
答:Allegro作者: atommann 时间: 2009-12-17 15:50
Nice, how much?作者: dspsharc 时间: 2009-12-17 16:48
to 【41楼】 shixm.zh
to 【42楼】 powu