我的cic滤波器的问题？附代码
--------三级CIC抽取器实例--------library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cic3_decimator IS
GENERIC (
STATE_HOLD :bit := '0';
STATE_SAMPLE :bit := '1');
PORT (
clk : IN bit; --输入时钟
x_in : IN std_logic_vector(7 DOWNTO 0); --输入8位数据
-- ComReg3 : inout std_logic_vector(25 DOWNTO 0);
y_out : OUT std_logic_vector(25 DOWNTO 0)); --输出26位数据
END cic3_decimator;
ARCHITECTURE translated OF cic3_decimator IS
-----------定义xhdl_2的类型
TYPE xhdl_2 IS ARRAY (2 DOWNTO 0) OF std_logic_vector(25 DOWNTO 0);
SIGNAL state :bit;
SIGNAL derived_clk :bit; ---下采样后的十时钟
SIGNAL counter :std_logic_vector(4 DOWNTO 0);
SIGNAL sxtx :std_logic_vector(25 DOWNTO 0);
SIGNAL x :std_logic_vector(7 DOWNTO 0);
SIGNAL IntReg :xhdl_2;
SIGNAL ComReg0 :xhdl_2;
SIGNAL ComReg1 :xhdl_2;
SIGNAL ComReg2 :xhdl_2;
SIGNAL ComReg3 :std_logic_vector(25 DOWNTO 0);
SIGNAL y_out_xhdl1 :std_logic_vector(25 DOWNTO 0);
BEGIN
y_out <= y_out_xhdl1;
----------实现下采样---------------
FSM_DECIMATOR : PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '0');
CASE state IS
WHEN STATE_HOLD => ---为0时如果counter=127，则state=1
IF (counter = "11111") THEN
state <= STATE_SAMPLE;
END IF;
WHEN STATE_SAMPLE =>---为1时，state=0，IntReg赋值给ComReg0
ComReg0 <= IntReg;
state <= STATE_HOLD;
WHEN OTHERS=> ---其他state=0
state <= STATE_HOLD;
END CASE;
IF ((counter > "01000") AND (counter < "10000")) THEN---8<counter<16
derived_clk <= '1'; ------生成下采样后的时钟----------
ELSE
derived_clk <= '0';
END IF;
counter <= counter + "00001";
END PROCESS;
---------符号扩展--------
sxtx <= "00" & x & x & x ;
------积分器实现模块--------
INTEGRATOR : PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1');
x <= x_in;
IntReg(0) <= IntReg(0) + sxtx;
IntReg(1) <= IntReg(1) + IntReg(0);
IntReg(2) <= IntReg(2) + IntReg(1);
END PROCESS;
--------梳状器实现模块-------
COMB : PROCESS
BEGIN
WAIT UNTIL (derived_clk'EVENT AND derived_clk = '1');
ComReg0(1) <= ComReg0(0);
ComReg0(2) <= ComReg0(1);
ComReg1(0) <= ComReg0(0) - ComReg0(2);
ComReg1(1) <= ComReg1(0);
ComReg1(2) <= ComReg1(1);
ComReg2(0) <= ComReg1(0) - ComReg1(2);
ComReg2(1) <= ComReg2(0);
ComReg2(2) <= ComReg2(1);
ComReg3 <= ComReg2(0) - ComReg2(2);
END PROCESS;
y_out <= ComReg3 ;
END translated;
提示Warning (10541): VHDL Signal Declaration warning at cic3_decimator.vhd(31): used implicit default value for signal "y_out_xhdl1" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. 正在学习滤波器，不知LZ是否突破了，呵呵！！
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