htjgdw 发表于 2017-3-8 11:04
老朋友,谢谢你的持续关注!
年后改好了一版,把之前的问题都fix了,增加了一个用户按键。其他还是老样子 ...
谢谢 htjgdw 兄的告知,您说的我都能理解,而我仍会持续的关注您的这个创作的。 {:handshake:}{:smile:}
能跑qt吗? make~~~~~~~~ 看着好,真想弄一个学习。 kingboy1000 发表于 2017-3-10 08:01
能跑qt吗?
能,但是现在板子的内存不够。如果我有时间,整一个LCD,再换上大一些的SDRAM可以试验一下。 最近翻出一片32M的SDRAM,焊到板上微调了一下时序,可以工作啦,cat /proc/meminfo 查看内存信息,还有21M剩余,很多啊! htjgdw 发表于 2017-3-28 13:19
最近翻出一片32M的SDRAM,焊到板上微调了一下时序,可以工作啦,cat /proc/meminfo 查看内存信息,还有21M ...
期待更多更新,持续关注中{:lol:} 情愿用老掉牙的ARM9 也不用这方案 楼主开源让我申手档也爽下 楼主历害呀 不明觉厉! soos 发表于 2017-3-28 18:29
楼主开源让我申手档也爽下
不用我开源,在www.emcraft.com网站有下载。 楼主可以玩玩全志V3S ,内部集成64MB ddr2 。 zxq1990 发表于 2017-4-15 10:57
楼主可以玩玩全志V3S ,内部集成64MB ddr2 。
看论坛里有一位朋友在玩,我就不玩了:) htjgdw 发表于 2017-4-17 11:08
看论坛里有一位朋友在玩,我就不玩了:)
大家一起玩,才好玩,资源共享,玩的花样也多 请问429移植后可以进入低功耗睡眠吗?
coolhorse 发表于 2017-4-19 16:32
请问429移植后可以进入低功耗睡眠吗?
最新的BSP可以的。我试验过,不过睡眠后就需要外部中断才能唤醒了很不方便(例子里是用外部按键),不知道能不能改用网络或者串口唤醒。 htjgdw 发表于 2017-3-13 14:56
能,但是现在板子的内存不够。如果我有时间,整一个LCD,再换上大一些的SDRAM可以试验一下。 ...
能用QT绝对是MCU工程师的福音,有时间要研究一下。谢谢楼主详尽资料和答复 楼主,你好,有兴趣一起研究下i.MX RT1050上跑uclinux吗? haso2007 发表于 2018-1-2 13:57
能用QT绝对是MCU工程师的福音,有时间要研究一下。谢谢楼主详尽资料和答复 ...
www.emcraft.com有STM32F7上运行的Qt Demo,你可以看一下。 Micro2008Chen 发表于 2018-1-3 10:31
楼主,你好,有兴趣一起研究下i.MX RT1050上跑uclinux吗?
i.MX RT 是0.65mm pitch的BGA封装,个人不容易搞定。 htjgdw 发表于 2018-1-3 14:50
i.MX RT 是0.65mm pitch的BGA封装,个人不容易搞定。
你指的是硬件制作难度吗? Micro2008Chen 发表于 2018-1-3 15:01
你指的是硬件制作难度吗?
对,是的,yes
以上只是为了凑字数,没别的意思。 有时间学习一下。{:smile:} htjgdw 发表于 2017-1-18 13:02
当然一样的,因为这货就是Linux,只不过在编译的时候选了no-MMU而已。
而且因为kernel比较新(4.2)驱动 ...
记得3.1以后的也用来设备树,请问4.2的设备树不一样吗?(还是有别的不同.) 这么搞有什么好处? 这个跑linux是不是还是有点费劲??? 感觉stm32f429跑uclinux很鸡肋的,这么贵的片子就跑了一个缩水版的Linux。 我一直很好奇F429得定位,大型得多媒体应该都是ARM9以上,控制类得话我觉得407也足够了 LVmcu 发表于 2018-4-20 20:04
记得3.1以后的也用来设备树,请问4.2的设备树不一样吗?(还是有别的不同.)
设备树没有区别,接近脚本语言,写法和参数都是与驱动相关的,没有完全统一的标准。 本帖最后由 htjgdw 于 2018-4-24 11:08 编辑
weidadejang 发表于 2018-4-20 21:34
这么搞有什么好处?
在没有操作系统的情况下,你写一个控制led的程序比如叫做LED,编译后需要烧到板子里就是了。如果你想换一个程序需要重新烧固件。
有了像Linux这样的操作系统,你同样写一个控制led的程序,编译后可以通过串口或网口下到板子里就可以执行./LED。再写其他的程序也是一样的只要你的板子有足够的存储空间。 牛人,赞一个 看着这板子流口水 ma买一块支持一下 楼主牛人啊 厉害了! 这个利害了。以前百为的板子可以运行LINUX
利害,顶起! 学习一下 乞巧楼头雁阵横,秦时月照古边城。 收藏一下, 弱弱的问一下楼主,linux的移植难度大不大? 顶一个。。谢谢分享 zxq7 发表于 2018-5-2 14:15
弱弱的问一下楼主,linux的移植难度大不大?
挺大的。这个Linux4.2移植到STM32F429上emcraft宣称有上千个工程师的贡献(应该指的是社区提交过代码的人数)。 不错,不错{:hug:} throg 发表于 2019-3-11 12:05
不错,不错
谢谢关注!
最近STM32MP157发布后,对STM32 linux感兴趣的人也多起来了。 问下楼主这个linux没有mmu是不是写的程序要自己管理sdram。就像写裸机一样不能写超量了? LVmcu 发表于 2019-5-11 21:07
问下楼主这个linux没有mmu是不是写的程序要自己管理sdram。就像写裸机一样不能写超量了? ...
大可不必这样操心。简单来说,只要你的程序使用的内存别超过实际物理内存就ok。
这应该是写程序最基本的要求了吧? 请问一下楼主,SDRAM采用32bit,移植修改uboot需要注意哪几个地方?我的硬件采用32bitSDRAM,修改测试不成功,主要表现在写内存发现,地址偏移0x20的数据相同,例如写0xd000 0000-0xd000 0010,发现0xd000 0020-0xd000 0030和前面想写的地址数据相同,实在头大了 小溪 发表于 2019-5-24 11:59
请问一下楼主,SDRAM采用32bit,移植修改uboot需要注意哪几个地方?我的硬件采用32bitSDRAM,修改测试不成功, ...
FMC寄存器设置改对了吗?
还有GPIO的AF设置检查一下。 本帖最后由 小溪 于 2019-6-9 11:25 编辑
htjgdw 发表于 2019-5-24 12:47
FMC寄存器设置改对了吗?
还有GPIO的AF设置检查一下。
搞得头大,可以百分百确认GPIO设置正确,基于以下情况说明,两种板子,一块内存配置地址是0xc0000000,一块是0xd0000000,在初始化内存函数结束位置写32字节数据并读出打印出来,一块板子正确,一块板子如上问题,只改了bank1和bank2区别的地方,都是在原来16位sdram基础上改的,主要改的是board.c文件接口重定义内存初始化和stm32discovery.h的内存首地址定义,出问题的是bank2定义0xd0000000 准备放弃了,怎么对照KEIL工程来设置,都不行,能改的都改了,贴一下我具体修改结果吧
1.修改文件\linux-cortexm-2.0.0\u-boot\board\stm\stm32f429-discovery\board.c
static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* Chip is LQFP144, see DM00077036.pdf for details */
/* 79, FMC_D31 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_10},
/* 78, FMC_D30 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_9},
/* 77, FMC_D29 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_7},
/* 68, FMC_D28 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_6},
/* 67, FMC_D27 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_3},
/* 66, FMC_D26 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_2},
/* 65, FMC_D25 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_1},
/* 64, FMC_D24 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_0},
/* 63, FMC_D23 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_15},
/* 60, FMC_D22 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_14},
/* 59, FMC_D21 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_13},
/* 58, FMC_D20 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_12},
/* 115, FMC_D19 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_11},
/* 114, FMC_D18 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_10},
/* 86, FMC_D17 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_9},
/* 85, FMC_D16 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_8},
/* 79, FMC_D15 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
/* 78, FMC_D14 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_9},
/* 77, FMC_D13 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_8},
/* 68, FMC_D12 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_15},
/* 67, FMC_D11 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_14},
/* 66, FMC_D10 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_13},
/* 65, FMC_D9 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_12},
/* 64, FMC_D8 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_11},
/* 63, FMC_D7 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_10},
/* 60, FMC_D6 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_9},
/* 59, FMC_D5 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_8},
/* 58, FMC_D4 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_7},
/* 115, FMC_D3 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_1},
/* 114, FMC_D2 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_0},
/* 86, FMC_D1 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_15},
/* 85, FMC_D0 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_14},
/* 142, FMC_NBL3 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_5}, // edit
/* 141, FMC_NBL2 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_4}, // edit
/* 142, FMC_NBL1 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_1},
/* 141, FMC_NBL0 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_0},
/* 90, FMC_A15, BA1 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_5},
/* 89, FMC_A14, BA0 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_4},
/* K15, FMC_A13 */
/* 87, FMC_A12 */
// {STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_2},// edit
/* 57, FMC_A11 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_1}, //A11
/* 56, FMC_A10 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_0},
/* 55, FMC_A9 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_15},
/* 54, FMC_A8 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_14},
/* 53, FMC_A7 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_13},
/* 50, FMC_A6 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_12},
/* 15, FMC_A5 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_5},
/* 14, FMC_A4 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_4},
/* 13, FMC_A3 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_3},
/* 12, FMC_A2 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_2},
/* 11, FMC_A1 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_1},
/* 10, FMC_A0 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
/* 136, SDRAM_NE */
//{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_6}, //SDNE1
//{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_6},
/* 49, SDRAM_NRAS */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_11},
/* 132, SDRAM_NCAS */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_15},
/* 26, SDRAM_NWE */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_0},
/* 135, SDRAM_CKE */
//{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_7}, //SDCKE1
//{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_5},
/* 93, SDRAM_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_8},
};
/*
* Following are timings for MT48LC32M16A2, from corresponding datasheet
*/
#define SDRAM_CAS 3
#define SDRAM_NB 1 /* Number of banks */
#define SDRAM_MWID 2 //32 bit W9812G2GH-6
//#define SDRAM_MWID 1 /* 16 bit memory */
//#define SDRAM_NR 0x2 /* 13-bit row */
#define SDRAM_NR 0x1 /* 12-bit row */ // edit
//#define SDRAM_NC 0x2 /* 10-bit col */
#define SDRAM_NC 0x0 /* 8-bit col */ // edit
int dram_init(void)
{u32 temp,ix;
u32 freq;
int rv;
u32 *pAddr;
u32 i;
u32 temp1;
u32 temp2;
/*
* Enable FMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FMC;
/*
* Get frequency for NS2CLK calculation.
*/
freq = clock_get(CLOCK_HCLK) / CONFIG_SYS_RAM_FREQ_DIV;
printf("clock_get(CLOCK_HCLK) = %ld\n",clock_get(CLOCK_HCLK));
printf("freq = %d\n",freq);
temp1 = STM32_SDRAM_FMC->sdcr1;
temp1 &= ((u32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
temp1 |= (u32)(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
0 << FMC_SDCR_RPIPE_SHIFT |
1 << FMC_SDCR_RBURST_SHIFT );
STM32_SDRAM_FMC->sdcr1= temp1;
printf("001 = 0X%08x\n",CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
SDRAM_NB << FMC_SDCR_NB_SHIFT |
SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
SDRAM_NR << FMC_SDCR_NR_SHIFT |
SDRAM_NC << FMC_SDCR_NC_SHIFT |
0 << FMC_SDCR_RPIPE_SHIFT |
1 << FMC_SDCR_RBURST_SHIFT
);
temp2 = STM32_SDRAM_FMC->sdcr2;
temp2 &= ((u32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
temp2 |= ((u32)(
// CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
SDRAM_NB << FMC_SDCR_NB_SHIFT |
SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
SDRAM_NR << FMC_SDCR_NR_SHIFT |
SDRAM_NC << FMC_SDCR_NC_SHIFT
// SDRAM_NC << FMC_SDCR_NC_SHIFT |
// 0 << FMC_SDCR_RPIPE_SHIFT |
// 1 << FMC_SDCR_RBURST_SHIFT
));
STM32_SDRAM_FMC->sdcr2 = temp2;
printf("002---STM32_SDRAM_FMC->sdcr2 = %x\n",STM32_SDRAM_FMC->sdcr2);
temp1 = STM32_SDRAM_FMC->sdtr1;
temp1 &= ((u32)~(FMC_SDTR1_TMRD| FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
FMC_SDTR1_TRC| FMC_SDTR1_TWR | FMC_SDTR1_TRP |
FMC_SDTR1_TRCD));
temp1 |= ((u32)(
SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TRC << FMC_SDTR_TRC_SHIFT
));
STM32_SDRAM_FMC->sdtr1 = temp1;
printf("033 = 0X%08x\n",SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
);
temp2 = STM32_SDRAM_FMC->sdtr2;
temp2 &= ((u32)~(FMC_SDTR1_TMRD| FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
FMC_SDTR1_TRC| FMC_SDTR1_TWR | FMC_SDTR1_TRP |
FMC_SDTR1_TRCD));
temp2 |= ((u32)(
SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
// SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
// SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
));
STM32_SDRAM_FMC->sdtr2 = temp2;
printf("003---STM32_SDRAM_FMC->sdtr2 = %x\n",STM32_SDRAM_FMC->sdtr2);
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK;
printf("004---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(200); /* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT();
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE;
printf("005---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
//STM32_SDRAM_FMC->sdcmr = (
// FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH |
// 7 << FMC_SDCMR_NRFS_SHIFT
//);
STM32_SDRAM_FMC->sdcmr = (
FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH |
7 << FMC_SDCMR_NRFS_SHIFT
);
printf("006---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
#define SDRAM_MODE_WB_SHIFT 9
//#define SDRAM_MODE_BL 0
#define SDRAM_MODE_BL 1
#define SDRAM_MODE_CAS SDRAM_CAS
#define SDRAM_MODE_WB 1
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 |
//(
// SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
// SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
//) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;
printf("077 = 0X%08x\n",FMC_SDCMR_BANK_2 |
(
SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
// SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT |
// SDRAM_MODE_WB << SDRAM_MODE_WB_SHIFT
) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE);
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 |
(
SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
// SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT |
// SDRAM_MODE_WB << SDRAM_MODE_WB_SHIFT
) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;
printf("007---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL;
printf("008---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
FMC_BUSY_WAIT();
/* Refresh timer */
STM32_SDRAM_FMC->sdrtr = SDRAM_TREF;
printf("009---STM32_SDRAM_FMC->sdrtr = %x\n",STM32_SDRAM_FMC->sdrtr);
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram.start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram.size= CONFIG_SYS_RAM_SIZE;
rv = 0;
cortex_m3_mpu_full_access();
dram_initialized = 1;
pAddr = (u32 *)0xd0001000;
printf("pAddr = %x\n",(u32)pAddr);
for(i=0;i<32;i++) //32
{
*((u32 *)(pAddr +i)) = 0xAB000000+i;
printf("pAddr +%d = %x = %x\n",i,(u32)pAddr +i,*((u32 *)(pAddr +i)));
}
for(i=0;i<32;i++)
{
printf("*0x%08x -> i=%d\n",((u32)pAddr+i),i);
printf("*0x%08x = 0x%08x\n",(pAddr+i),*((u32 *)(pAddr +i)));
}
pAddr = (u32 *)0xd0001100;
for(i=0;i<8;i++)
{
*((u32 *)(pAddr +i)) = 0xAB000000+i;
printf("pAddr +%d = %x = %x\n",i,(u32)pAddr +i,*((u32 *)(pAddr +i)));
}
for(i=0;i<32;i++)
{
printf("*0x%08x -> i=%d\n",((u32)pAddr+i),i);
printf("*0x%08x = 0x%08x\n",((u32)pAddr+i),*((u32 *)(pAddr +i)));
}
return rv;
}
2.修改文件\linux-cortexm-2.0.0\u-boot\include\configs\stm32f429-discovery.h
#define CONFIG_NR_DRAM_BANKS 1
//#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
//#define CONFIG_SYS_RAM_SIZE (4 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
//#define CONFIG_SYS_RAM_BASE 0xC0000000
#define CONFIG_SYS_RAM_BASE 0xD0000000
流口水啊。
这么一套硬件成本下来得多少米?
楼主有详细开发教程嘛?
页:
1
[2]