quartus modelsim联合仿真出现问题，求教...... (amobbs.com 阿莫电子技术论坛) -

lqf2060 发表于 2014-11-17 16:47:03

quartus modelsim联合仿真出现问题，求教......

错误提示如下：
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps tb
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: Failed to find design unit work.tb.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./xinhao_run_msim_rtl_verilog.do PAUSED at line 40

/xinhao_run_msim_rtl_verilog.do第40行为：
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" tb
testbench 检查过没有错误。

steven0419 发表于 2014-12-3 17:17:46

整个编译的信息贴出来看看呢，还是肯定代码里面有错，编译不通过而已

lqf2060 发表于 2014-12-3 17:48:05

steven0419 发表于 2014-12-3 17:17
整个编译的信息贴出来看看呢，还是肯定代码里面有错，编译不通过而已

不知道要复制那些，就把modlesim里面的全部复制过来了
# Reading D:/modeltech_6.5/tcl/vsim/pref.tcl
# //ModelSim SE 6.5 Jan 22 2009
# //
# //Copyright 1991-2009 Mentor Graphics Corporation
# //          All Rights Reserved.
# //
# //THIS WORK CONTAINS TRADE SECRET AND
# //PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //AND IS SUBJECT TO LICENSE TERMS.
# //
# do xinhao_run_msim_rtl_verilog.do
# if ! {
# file mkdir verilog_libs
# }
#
# vlib verilog_libs/altera_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_ver".
# vmap altera_ver ./verilog_libs/altera_ver
# Copying D:\modeltech_6.5\win32/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\modeltech_6.5\win32/../modelsim.ini to modelsim.ini.
#       Updated modelsim.ini.
# vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module global
# -- Compiling module carry
# -- Compiling module cascade
# -- Compiling module carry_sum
# -- Compiling module exp
# -- Compiling module soft
# -- Compiling module opndrn
# -- Compiling module row_global
# -- Compiling module TRI
# -- Compiling module lut_input
# -- Compiling module lut_output
# -- Compiling module latch
# -- Compiling module dlatch
# -- Compiling module prim_gdff
# -- Compiling module dff
# -- Compiling module dffe
# -- Compiling module dffea
# -- Compiling module dffeas
# -- Compiling module prim_gtff
# -- Compiling module tff
# -- Compiling module tffe
# -- Compiling module prim_gjkff
# -- Compiling module jkff
# -- Compiling module jkffe
# -- Compiling module prim_gsrff
# -- Compiling module srff
# -- Compiling module srffe
# -- Compiling module clklock
# -- Compiling module alt_inbuf
# -- Compiling module alt_outbuf
# -- Compiling module alt_outbuf_tri
# -- Compiling module alt_iobuf
# -- Compiling module alt_inbuf_diff
# -- Compiling module alt_outbuf_diff
# -- Compiling module alt_outbuf_tri_diff
# -- Compiling module alt_iobuf_diff
# -- Compiling module alt_bidir_diff
# -- Compiling module alt_bidir_buf
# -- Compiling UDP PRIM_GDFF_LOW
# -- Compiling UDP PRIM_GDFF_HIGH
#
# Top level modules:
# global
# carry
# cascade
# carry_sum
# exp
# soft
# opndrn
# row_global
# TRI
# lut_input
# lut_output
# latch
# dlatch
# dff
# dffe
# dffea
# dffeas
# tff
# tffe
# jkff
# jkffe
# srff
# srffe
# clklock
# alt_inbuf
# alt_outbuf
# alt_outbuf_tri
# alt_iobuf
# alt_inbuf_diff
# alt_outbuf_diff
# alt_outbuf_tri_diff
# alt_iobuf_diff
# alt_bidir_diff
# alt_bidir_buf
#
# vlib verilog_libs/lpm_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/lpm_ver".
# vmap lpm_ver ./verilog_libs/lpm_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module LPM_MEMORY_INITIALIZATION
# -- Compiling module LPM_HINT_EVALUATION
# -- Compiling module LPM_DEVICE_FAMILIES
# -- Compiling module lpm_constant
# -- Compiling module lpm_inv
# -- Compiling module lpm_and
# -- Compiling module lpm_or
# -- Compiling module lpm_xor
# -- Compiling module lpm_bustri
# -- Compiling module lpm_mux
# -- Compiling module lpm_decode
# -- Compiling module lpm_clshift
# -- Compiling module lpm_add_sub
# -- Compiling module lpm_compare
# -- Compiling module lpm_mult
# -- Compiling module lpm_divide
# -- Compiling module lpm_abs
# -- Compiling module lpm_counter
# -- Compiling module lpm_latch
# -- Compiling module lpm_ff
# -- Compiling module lpm_shiftreg
# -- Compiling module lpm_ram_dq
# -- Compiling module lpm_ram_dp
# -- Compiling module lpm_ram_io
# -- Compiling module lpm_rom
# -- Compiling module lpm_fifo
# -- Compiling module lpm_fifo_dc_dffpipe
# -- Compiling module lpm_fifo_dc_fefifo
# -- Compiling module lpm_fifo_dc_async
# -- Compiling module lpm_fifo_dc
# -- Compiling module lpm_inpad
# -- Compiling module lpm_outpad
# -- Compiling module lpm_bipad
#
# Top level modules:
# lpm_constant
# lpm_inv
# lpm_and
# lpm_or
# lpm_xor
# lpm_bustri
# lpm_mux
# lpm_decode
# lpm_clshift
# lpm_add_sub
# lpm_compare
# lpm_mult
# lpm_divide
# lpm_abs
# lpm_counter
# lpm_latch
# lpm_ff
# lpm_shiftreg
# lpm_ram_dq
# lpm_ram_dp
# lpm_ram_io
# lpm_rom
# lpm_fifo
# lpm_fifo_dc
# lpm_inpad
# lpm_outpad
# lpm_bipad
#
# vlib verilog_libs/sgate_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/sgate_ver".
# vmap sgate_ver ./verilog_libs/sgate_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module oper_add
# -- Compiling module oper_addsub
# -- Compiling module mux21
# -- Compiling module io_buf_tri
# -- Compiling module io_buf_opdrn
# -- Compiling module oper_mult
# -- Compiling module tri_bus
# -- Compiling module oper_div
# -- Compiling module oper_mod
# -- Compiling module oper_left_shift
# -- Compiling module oper_right_shift
# -- Compiling module oper_rotate_left
# -- Compiling module oper_rotate_right
# -- Compiling module oper_less_than
# -- Compiling module oper_mux
# -- Compiling module oper_selector
# -- Compiling module oper_decoder
# -- Compiling module oper_bus_mux
# -- Compiling module oper_latch
#
# Top level modules:
# oper_add
# oper_addsub
# mux21
# io_buf_tri
# io_buf_opdrn
# oper_mult
# tri_bus
# oper_div
# oper_mod
# oper_left_shift
# oper_right_shift
# oper_rotate_left
# oper_rotate_right
# oper_less_than
# oper_mux
# oper_selector
# oper_decoder
# oper_bus_mux
# oper_latch
#
# vlib verilog_libs/altera_mf_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_mf_ver".
# vmap altera_mf_ver ./verilog_libs/altera_mf_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module MF_cycloneiiigl_m_cntr
# -- Compiling module MF_cycloneiiigl_n_cntr
# -- Compiling module MF_cycloneiiigl_scale_cntr
# -- Compiling module cycloneiiigl_post_divider
# -- Compiling module MF_cycloneiiigl_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module alt3pram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle
# -- Compiling module alt_cal
# -- Compiling module alt_cal_mm
# -- Compiling module alt_cal_c3gxb
# -- Compiling module alt_cal_sv
# -- Compiling module alt_aeq_s4
# -- Compiling module alt_eyemon
# -- Compiling module alt_dfe
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module sld_virtual_jtag_basic
# -- Compiling module altsource_probe
#
# Top level modules:
# lcell
# altpll
# altlvds_rx
# altlvds_tx
# dcfifo
# altaccumulate
# altmult_accum
# altmult_add
# altfp_mult
# altsqrt
# altclklock
# altddio_bidir
# altdpram
# alt3pram
# parallel_add
# scfifo
# altshift_taps
# a_graycounter
# altsquare
# altera_std_synchronizer_bundle
# alt_cal
# alt_cal_mm
# alt_cal_c3gxb
# alt_cal_sv
# alt_aeq_s4
# alt_eyemon
# alt_dfe
# sld_virtual_jtag
# sld_signaltap
# altstratixii_oct
# altparallel_flash_loader
# altserial_flash_loader
# sld_virtual_jtag_basic
# altsource_probe
#
# vlib verilog_libs/altera_lnsim_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_lnsim_ver".
# vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
# Modifying modelsim.ini
# vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module altera_pll
# -- Compiling package altera_lnsim_functions
# -- Compiling module generic_pll
# -- Importing package altera_lnsim_functions
# -- Compiling module generic_cdr
# -- Compiling module common_28nm_ram_pulse_generator
# -- Compiling module common_28nm_ram_register
# -- Compiling module common_28nm_ram_block
# -- Compiling module generic_m20k
# -- Compiling module generic_m10k
# -- Compiling module common_28nm_mlab_cell_pulse_generator
# -- Compiling module common_28nm_mlab_cell
# -- Compiling module generic_mlab_cell
# -- Compiling module generic_mux
# -- Compiling module generic_device_pll
# -- Compiling module altera_mult_add
# -- Compiling module ama_signed_extension_function
# -- Compiling module ama_dynamic_signed_function
# -- Compiling module ama_register_function
# -- Compiling module ama_register_with_ext_function
# -- Compiling module ama_data_split_reg_ext_function
# -- Compiling module ama_coef_reg_ext_function
# -- Compiling module ama_adder_function
# -- Compiling module ama_multiplier_function
# -- Compiling module ama_preadder_function
# -- Compiling module ama_accumulator_function
# -- Compiling module ama_systolic_adder_function
# -- Compiling module ama_scanchain
#
# Top level modules:
# altera_pll
# generic_cdr
# generic_m20k
# generic_m10k
# generic_mlab_cell
# generic_mux
# generic_device_pll
# altera_mult_add
#
# vlib verilog_libs/cycloneive_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/cycloneive_ver".
# vmap cycloneive_ver ./verilog_libs/cycloneive_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work cycloneive_ver {d:/altera/11.0/quartus/eda/sim_lib/cycloneive_atoms.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling UDP CYCLONEIVE_PRIM_DFFE
# -- Compiling UDP CYCLONEIVE_PRIM_DFFEAS
# -- Compiling UDP CYCLONEIVE_PRIM_DFFEAS_HIGH
# -- Compiling module cycloneive_dffe
# -- Compiling module cycloneive_mux21
# -- Compiling module cycloneive_mux41
# -- Compiling module cycloneive_and1
# -- Compiling module cycloneive_and16
# -- Compiling module cycloneive_bmux21
# -- Compiling module cycloneive_b17mux21
# -- Compiling module cycloneive_nmux21
# -- Compiling module cycloneive_b5mux21
# -- Compiling module cycloneive_latch
# -- Compiling module cycloneive_routing_wire
# -- Compiling module cycloneive_m_cntr
# -- Compiling module cycloneive_n_cntr
# -- Compiling module cycloneive_scale_cntr
# -- Compiling module cycloneive_pll_reg
# -- Compiling module cycloneive_pll
# -- Compiling module cycloneive_lcell_comb
# -- Compiling module cycloneive_ff
# -- Compiling module cycloneive_ram_pulse_generator
# -- Compiling module cycloneive_ram_register
# -- Compiling module cycloneive_ram_block
# -- Compiling module cycloneive_mac_data_reg
# -- Compiling module cycloneive_mac_sign_reg
# -- Compiling module cycloneive_mac_mult_internal
# -- Compiling module cycloneive_mac_mult
# -- Compiling module cycloneive_mac_out
# -- Compiling module cycloneive_io_ibuf
# -- Compiling module cycloneive_io_obuf
# -- Compiling module cycloneive_ddio_out
# -- Compiling module cycloneive_ddio_oe
# -- Compiling module cycloneive_pseudo_diff_out
# -- Compiling module cycloneive_io_pad
# -- Compiling module cycloneive_ena_reg
# -- Compiling module cycloneive_clkctrl
# -- Compiling module cycloneive_rublock
# -- Compiling module cycloneive_apfcontroller
# -- Compiling module cycloneive_termination_ctrl
# -- Compiling module cycloneive_termination_rupdn
# -- Compiling module cycloneive_termination
# -- Compiling module cycloneive_jtag
# -- Compiling module cycloneive_crcblock
# -- Compiling module cycloneive_oscillator
#
# Top level modules:
# cycloneive_dffe
# cycloneive_and1
# cycloneive_and16
# cycloneive_bmux21
# cycloneive_b17mux21
# cycloneive_nmux21
# cycloneive_b5mux21
# cycloneive_routing_wire
# cycloneive_pll_reg
# cycloneive_pll
# cycloneive_lcell_comb
# cycloneive_ff
# cycloneive_ram_block
# cycloneive_mac_mult
# cycloneive_mac_out
# cycloneive_io_ibuf
# cycloneive_io_obuf
# cycloneive_ddio_out
# cycloneive_ddio_oe
# cycloneive_pseudo_diff_out
# cycloneive_io_pad
# cycloneive_clkctrl
# cycloneive_rublock
# cycloneive_apfcontroller
# cycloneive_termination
# cycloneive_jtag
# cycloneive_crcblock
# cycloneive_oscillator
#
# if {} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying modelsim.ini
#
# vlog -vlog01compat -work work +incdir+D:/yaoqiuboxing/source {D:/yaoqiuboxing/source/top.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module xinhao
#
# Top level modules:
# xinhao
# vlog -vlog01compat -work work +incdir+D:/yaoqiuboxing/source {D:/yaoqiuboxing/source/boxing.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module boxing
#
# Top level modules:
# boxing
# vlog -vlog01compat -work work +incdir+D:/yaoqiuboxing/source {D:/yaoqiuboxing/source/beipin_100MHZ.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module beipin_100MHZ
#
# Top level modules:
# beipin_100MHZ
# vlog -vlog01compat -work work +incdir+D:/yaoqiuboxing/db {D:/yaoqiuboxing/db/beipin_100mhz_altpll.v}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module beipin_100MHZ_altpll
#
# Top level modules:
# beipin_100MHZ_altpll
#
# vlog -vlog01compat -work work +incdir+D:/yaoqiuboxing/simulation/modelsim {D:/yaoqiuboxing/simulation/modelsim/xinhao.vt}
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module xinhao_vlg_tst
#
# Top level modules:
# xinhao_vlg_tst
#
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps tb
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: Failed to find design unit work.tb.
# Optimization failed
# Error loading design
# Error: Error loading design
#    Pausing macro execution
# MACRO ./xinhao_run_msim_rtl_verilog.do PAUSED at line 43

Nuker 发表于 2014-12-4 12:35:13

错误描述十分十分十分清楚：
# ** Error: Failed to find design unit work.tb

LZ的顶层模块是xinhao_vlg_tst还是tb？没弄清楚改动会产生什么影响的时候千万不要随意改代码！
# Top level modules:
# xinhao_vlg_tst

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quartus modelsim联合仿真出现问题，求教......