关于PLL时钟的警告
生成了两个PLL时钟，用的是同一个时钟源，可是查看报告却是这样的，一个signal tap是专用的，另外一个却是全局的 并且报了警告 Warning (15055): PLL "PLL2:b2v_inst20|altpll:altpll_component|PLL2_altpll:auto_generated|pll1" input clock inclk is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input Info (15024): Input port INCLK of node "PLL2:b2v_inst20|altpll:altpll_component|PLL2_altpll:auto_generated|pll1" is driven by FPGA_CLK~inputclkctrl which is OUTCLK output port of Clock control block type node FPGA_CLK~inputclkctrl
页:
[1]