小白求救，关于Quartus的waring（10240）
本人正在FPGA入门道路上裸奔的小白一枚，写了一段流水灯代码，四种流动模式，其中一种是来回流动的那种，但是总是出现这两行警告，接上LED灯之后输出还不对Warning (10240): Verilog HDL Always Construct warning at runhorse_led_4_2.v(95): inferring latch(es) for variable "loop_bit_A", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at runhorse_led_4_2.v(95): inferring latch(es) for variable "counter_A", which holds its previous value in one or more paths through the always construct
下面是出问题的那段代码，求大大们指教啊，我已经快要被逼疯了{:mad:}{:mad:}
always @ (posedge clk_led_in or negedge rst)
begin
case (SW_AB_led)
model0:
begin
decoder_2_4 (counter_A, led_data_r);
if (!rst)
begin
loop_bit_A = 1'b0;
counter_A = 2'b0;
end
else if (loop_bit_A)
begin
counter_A = counter_A + 1'b1;
if (counter_A==2'b11)
loop_bit_A = 1'b0;
end
else
begin
counter_A = counter_A - 1'b1;
if (counter_A==2'b0)
loop_bit_A = 1'b0;
end
end
我在外面定义了一个2-4译码器的任务，就是“decoder_2_4 (counter_A, led_data_r);”那行，我的想法是只要counter_A在2’b0到2‘b11之间来回跑就行了，但是~~~~~~~{:cry:}{:cry:}
counter_A在多个 always @ (posedge clk_led_in or negedge rst)
中被赋值了，一个变量只能在一个 always中被赋值
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