关于一个VHDL元件例化写全加器的程序
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY or2 IS
PORT(a,b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END ENTITY or2;
ARCHITECTURE one OF or2 IS
BEGIN
c <= a OR b;
END ARCHITECTURE one;
-------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY h_adder IS
PORT(a,b: IN STD_LOGIC;
co,so: OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE two OF h_adder IS
BEGIN
co <= (a OR b)AND(a NAND b);
so <= NOT(a NAND b);
END ARCHITECTURE two;
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY f_adder IS
PORT(ain,bin,cin: IN STD_LOGIC;
cout,sum: OUT STD_LOGIC);
END ENTITY f_adder;
ARCHITECTURE three OF f_adder IS
COMPONENT h_adder
PORT(a,b: IN STD_LOGIC;
co,so: OUT STD_LOGIC);
END COMPONENT h_adder;
COMPONENT or2
PORT(a,b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END COMPONENT or2;
SIGNAL d,e,f:STD_LOGIC;
BEGIN
u1:h_adder PORT MAP(a=>ain, b=>bin, co=>d, so=>e);
u2:h_adder PORT MAP(a=>e, b=>cin, co=>f, so=>sum);
u3:or2 PORT MAP(a=>d, b=>f, c=>cout);
END ARCHITECTURE three;
报警说：Symbolic name "a" is not a port of "or2" in a VHDL Design File
Symbolic name "b" is not a port of "or2" in a VHDL Design File
Symbolic name "c" is not a port of "or2" in a VHDL Design File
程序单独摘出来都没有任何问题，估计问题是在元件例化那。
这个程序是教科书上原封不动打下来的。
估计用过这本书（电子科大出版社的）的大神应该知道错在哪？
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