如何用modelsim_altera对sdram或者usb等进行仿真？
可以用modelsim_altera对具体的具体的有输入输出的元器件进行仿真么？ 本帖最后由 zcy0517 于 2014-4-7 14:59 编辑下面程序是一个modelsim仿真的程序吗？我觉得好奇怪啊~~~ 怎么又input output 又有initial呢？
module sdram_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output[ 15: 0] q;
input [ 15: 0] data;
input [ 21: 0] rdaddress;
input rdclken;
input [ 21: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array ;
wire [ 15: 0] q;
reg [ 21: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array;
initial
$readmemh("sdram.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
//lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
//defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 22,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
页:
[1]