请问有用Cyclone4写过PLL的吗?想求个例程
自己设置的PLL,下载到开发板上没法用啊...............(是我哪里设置错了么){:mad:}module PLL_Inst (sys_clk,sys_rst_n,clk_100M,clk_20M,clk_80M);
input sys_clk ; //system clock;
input sys_rst_n ; //system reset, low is active;
output clk_100M ; //output clock 100M;
output clk_20M ; //output clock 20M;
output clk_80M ; //output clock 80M;
wire clk_100M_tmp ; //wire clock 100M;
wire clk_80M_tmp ; //wire clock 20M;
wire clk_20M_tmp ; //wire clock 80M;
wire clk_100M ; //wire clock 100M;
wire clk_80M ; //wire clock 20M;
wire clk_20M ; //wire clock 80M;
parameter WIDTH = 8;
parameter SIZE= 8;
PLL PLL_U0 (
.areset(sys_rst_n ) ,
.inclk0(sys_clk ) ,
.c0 (clk_100M_tmp ) ,
.c1 (clk_20M_tmp ) ,
.c2 (clk_80M_tmp ) ,
.locked(clock_enbale )
);
assign clk_100M = (clock_enbale == 1'b1)? clk_100M_tmp : 1'b0;
assign clk_80M= (clock_enbale == 1'b1)? clk_80M_tmp: 1'b0;
assign clk_20M= (clock_enbale == 1'b1)? clk_20M_tmp: 1'b0;
endmodule PLL IP核 是高电平复位,请多看该IP核手册 呵呵,PLL的复位信号是areset ,而你例化的是areset
知道原因了吧 大神{:handshake:}
谢谢两位了
页:
[1]