FPGA三段式状态机为啥多出几条信号线。。
本帖最后由 深海烟花 于 2013-10-9 12:58 编辑不知道为什么我的状态机中没有 IDLE -> WAIT ;CMD_S1 ->WAIT ;ERROR ->WAIT的状态转移，综合出来的状态机却存在，这是什么问题，求解？
module cmd_top(clk,rst_n,data_start,led,cmd_in,cmd_out,tx_en,buzer,camer_start,tuoluo_start,cmd_reg);
input clk,rst_n;
input data_start;
input cmd_in;
output cmd_out;
output tx_en;
output led;
output buzer;
output camer_start;
output tuoluo_start; // tuoluo tx_datastart
output cmd_reg;
/*................................................*/
reg led;
reg cmd_out;
reg tx_en;
reg camer_startr;
reg tuoluo_start;
reg buzer;
reg cmd_reg;
reg cmd_reg0;
reg cmd_reg1;
reg cmd_reg2;
reg cmd_reg3;
reg cmd_reg4;
/*..............................................*/
reg cstate;
reg nstate;
parameter ERROR = 16'b0000_0000_0000_0000,
IDLE = 16'b0000_0000_0000_0001,
CMD_S1 = 16'b0000_0000_0000_0010,
LED_ON = 16'b0000_0000_0000_0100,
LED_OFF = 16'b0000_0000_0000_1000,
IMAGE = 16'b0000_0000_0001_0000,
BUZZER_ON = 16'b0000_0000_0010_0000,
BUZZER_OFF = 16'b0000_0000_0100_0000,
TUOLUO_ON = 16'b0000_0000_1000_0000,
TUOLUO_OFF = 16'b0000_0001_0000_0000,
CHANNEL_CALL = 16'b0000_0010_0000_0000,
GNC_POW = 16'b0000_0100_0000_0000,
OBC_POW = 16'b0000_1000_0000_0000,
DATA_POW = 16'b0001_0000_0000_0000,
FIRE_POW = 16'b0010_0000_0000_0000,
TRI_POW = 16'b0100_0000_0000_0000,
WAIT = 16'b1000_0000_0000_0000;
/*.............................................*/
reg cnt_4cly;
always@(negedge rst_n or posedge clk)
if(!rst_n) cnt_4cly <= 2'd0;
else if(nstate == WAIT) cnt_4cly <= cnt_4cly + 1'b1;
else cnt_4cly <= 2'd0;
wire delay_4cly = (cnt_4cly == 2'b11);
/*................................................*/
always@(posedge clk or negedge rst_n)
if(!rst_n) cstate <= IDLE;
else cstate <= nstate;
always@(cstate or data_start or cmd_in or delay_4cly)
begin
case(cstate)
IDLE: if(data_start) nstate = CMD_S1;
else nstate = IDLE;
CMD_S1: begin case(cmd_in)
8'b1010_0000: nstate = CHANNEL_CALL;
8'b1100_0000: nstate = IMAGE;
8'b1101_1001: nstate = TUOLUO_ON;
8'b1101_1000: nstate = TUOLUO_OFF;
8'b1110_0001: nstate = LED_ON;
8'b1110_0010: nstate = LED_OFF;
8'b1110_0011: nstate = BUZZER_ON;
8'b1110_0100: nstate = BUZZER_OFF;
8'b1111_1000: nstate = GNC_POW;
8'b1111_1001: nstate = OBC_POW;
8'b1111_1010: nstate = DATA_POW;
8'b1111_1011: nstate = FIRE_POW;
8'b1111_1100: nstate = TRI_POW;
default: nstate = ERROR;
endcase
end
ERROR: nstate = IDLE;
CHANNEL_CALL: nstate = WAIT;
IMAGE: nstate = WAIT;
TUOLUO_ON: nstate = WAIT;
TUOLUO_OFF: nstate = WAIT;
LED_ON: nstate = WAIT;
LED_OFF: nstate = WAIT;
BUZZER_ON: nstate = WAIT;
BUZZER_OFF: nstate = WAIT;
GNC_POW: nstate = WAIT;
OBC_POW: nstate = WAIT;
DATA_POW: nstate = WAIT;
FIRE_POW: nstate = WAIT;
TRI_POW: nstate = WAIT;
WAIT:if(delay_4cly) nstate = IDLE;
else nstate = WAIT;
default: nstate = IDLE;
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
tx_en <= 1'd0;
led<=4'd0;
cmd_out<=8'd0;
camer_startr<=1'd0;
tuoluo_start<=1'd0;
buzer <= 1'd0;
cmd_reg0 <= 8'b1110_0001;
cmd_reg1 <= 8'b1110_0010;
cmd_reg2 <= 8'b1110_0100;
cmd_reg3 <= 8'b1110_1000;
cmd_reg4 <= 8'b1111_0000;
end
else case(nstate)
IDLE: begin
tx_en <= 1'd0;
led<=4'd0;
cmd_out<=8'd0;
camer_startr<=1'd0;
tuoluo_start<=1'd0;
buzer <= 1'd0;
end
CHANNEL_CALL:begin
tx_en<=1'd1;
cmd_out<=8'b1010_0000;
end
IMAGE:begin
camer_startr<=1'b1;
led<=1;
tx_en<=1'd1;
cmd_out<=8'b0100_0000;
end
TUOLUO_ON:begin
tuoluo_start<=1'd1;
cmd_reg<=8'b1101_1001;
tx_en<=1'd0;
end
TUOLUO_OFF:begin
tuoluo_start<=1'd0;
cmd_reg<=8'b1101_1000;
tx_en<=1'd1;
cmd_out<=8'b1101_1000;
end
LED_ON:begin
led<=4'b1111;
tx_en<=1'd1;
cmd_out<=8'b1110_0001;
end
LED_OFF:begin
led<=4'd0;
tx_en<=1'd1;
cmd_out<=8'b1110_0010;
end
BUZZER_ON:begin
buzer=1'd1;
tx_en<=1'd1;
cmd_out<=8'b1110_0011;
end
BUZZER_OFF:begin
buzer<=1'd0;
tx_en<=1'd1;
cmd_out<=8'b1110_0100;
end
GNC_POW:begin
cmd_reg0<=cmd_reg0^8'b0000_0001;
cmd_reg <= cmd_reg0;tx_en<=1'd0;
end
OBC_POW:begin
cmd_reg1<=cmd_reg1^8'b0000_0010;
cmd_reg <= cmd_reg1;tx_en<=1'd0;
end
DATA_POW:begin
cmd_reg2<=cmd_reg2^8'b0000_0100;
cmd_reg <= cmd_reg2;tx_en<=1'd0;
end
FIRE_POW:begin
cmd_reg3<=cmd_reg3^8'b0000_1000;
cmd_reg <= cmd_reg3;tx_en<=1'd0;
end
TRI_POW:begin
cmd_reg4<=cmd_reg4^8'b0001_0000;
cmd_reg <= cmd_reg4;tx_en<=1'd0;
end
ERROR:begin
led <= 4'b1010;
tx_en<=1'd1;
cmd_out<=8'b1111_1111;
end
WAIT:;
//tx_en <= 1'd0;
//camer_startr<=1'd0;
default: ;
endcase
assign camer_start = camer_startr;
endmodule
module cmd_top(clk,rst_n,data_start,led,cmd_in,cmd_out,tx_en,buzer,camer_start,tuoluo_start,cmd_reg);
input clk,rst_n;
input data_start;
input cmd_in;
output cmd_out;
output tx_en;
output led;
output buzer;
output camer_start;
output tuoluo_start; // tuoluo tx_datastart
output cmd_reg;
/*................................................*/
reg led;
reg cmd_out;
reg tx_en;
reg camer_startr;
reg tuoluo_start;
reg buzer;
reg cmd_reg;
reg cmd_reg0;
reg cmd_reg1;
reg cmd_reg2;
reg cmd_reg3;
reg cmd_reg4;
/*..............................................*/
reg cstate;
reg nstate;
parameter ERROR = 16'b0000_0000_0000_0000,
IDLE = 16'b0000_0000_0000_0001,
CMD_S1 = 16'b0000_0000_0000_0010,
LED_ON = 16'b0000_0000_0000_0100,
LED_OFF = 16'b0000_0000_0000_1000,
IMAGE = 16'b0000_0000_0001_0000,
BUZZER_ON = 16'b0000_0000_0010_0000,
BUZZER_OFF = 16'b0000_0000_0100_0000,
TUOLUO_ON = 16'b0000_0000_1000_0000,
TUOLUO_OFF = 16'b0000_0001_0000_0000,
CHANNEL_CALL = 16'b0000_0010_0000_0000,
GNC_POW = 16'b0000_0100_0000_0000,
OBC_POW = 16'b0000_1000_0000_0000,
DATA_POW = 16'b0001_0000_0000_0000,
FIRE_POW = 16'b0010_0000_0000_0000,
TRI_POW = 16'b0100_0000_0000_0000,
WAIT = 16'b1000_0000_0000_0000;
/*.............................................*/
reg cnt_4cly;
always@(negedge rst_n or posedge clk)
if(!rst_n) cnt_4cly <= 2'd0;
else if(nstate == WAIT) cnt_4cly <= cnt_4cly + 1'b1;
else cnt_4cly <= 2'd0;
wire delay_4cly = (cnt_4cly == 2'b11);
/*................................................*/
always@(posedge clk or negedge rst_n)
if(!rst_n) cstate <= IDLE;
else cstate <= nstate;
always@(cstate or data_start or cmd_in or delay_4cly)
begin
case(cstate)
IDLE: if(data_start) nstate = CMD_S1;
else nstate = IDLE;
CMD_S1: begin case(cmd_in)
8'b1010_0000: nstate = CHANNEL_CALL;
8'b1100_0000: nstate = IMAGE;
8'b1101_1001: nstate = TUOLUO_ON;
8'b1101_1000: nstate = TUOLUO_OFF;
8'b1110_0001: nstate = LED_ON;
8'b1110_0010: nstate = LED_OFF;
8'b1110_0011: nstate = BUZZER_ON;
8'b1110_0100: nstate = BUZZER_OFF;
8'b1111_1000: nstate = GNC_POW;
8'b1111_1001: nstate = OBC_POW;
8'b1111_1010: nstate = DATA_POW;
8'b1111_1011: nstate = FIRE_POW;
8'b1111_1100: nstate = TRI_POW;
default: nstate = ERROR;
endcase
end
ERROR: nstate = IDLE;
CHANNEL_CALL: nstate = WAIT;
IMAGE: nstate = WAIT;
TUOLUO_ON: nstate = WAIT;
TUOLUO_OFF: nstate = WAIT;
LED_ON: nstate = WAIT;
LED_OFF: nstate = WAIT;
BUZZER_ON: nstate = WAIT;
BUZZER_OFF: nstate = WAIT;
GNC_POW: nstate = WAIT;
OBC_POW: nstate = WAIT;
DATA_POW: nstate = WAIT;
FIRE_POW: nstate = WAIT;
TRI_POW: nstate = WAIT;
WAIT:if(delay_4cly) nstate = IDLE;
else nstate = WAIT;
default: nstate = IDLE;
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
tx_en <= 1'd0;
led<=4'd0;
cmd_out<=8'd0;
camer_startr<=1'd0;
tuoluo_start<=1'd0;
buzer <= 1'd0;
cmd_reg0 <= 8'b1110_0001;
cmd_reg1 <= 8'b1110_0010;
cmd_reg2 <= 8'b1110_0100;
cmd_reg3 <= 8'b1110_1000;
cmd_reg4 <= 8'b1111_0000;
end
else case(nstate)
IDLE: begin
tx_en <= 1'd0;
led<=4'd0;
cmd_out<=8'd0;
camer_startr<=1'd0;
tuoluo_start<=1'd0;
buzer <= 1'd0;
end
CHANNEL_CALL:begin
tx_en<=1'd1;
cmd_out<=8'b1010_0000;
end
IMAGE:begin
camer_startr<=1'b1;
led<=1;
tx_en<=1'd1;
cmd_out<=8'b0100_0000;
end
TUOLUO_ON:begin
tuoluo_start<=1'd1;
cmd_reg<=8'b1101_1001;
tx_en<=1'd0;
end
TUOLUO_OFF:begin
tuoluo_start<=1'd0;
cmd_reg<=8'b1101_1000;
tx_en<=1'd1;
cmd_out<=8'b1101_1000;
end
LED_ON:begin
led<=4'b1111;
tx_en<=1'd1;
cmd_out<=8'b1110_0001;
end
LED_OFF:begin
led<=4'd0;
tx_en<=1'd1;
cmd_out<=8'b1110_0010;
end
BUZZER_ON:begin
buzer=1'd1;
tx_en<=1'd1;
cmd_out<=8'b1110_0011;
end
BUZZER_OFF:begin
buzer<=1'd0;
tx_en<=1'd1;
cmd_out<=8'b1110_0100;
end
GNC_POW:begin
cmd_reg0<=cmd_reg0^8'b0000_0001;
cmd_reg <= cmd_reg0;tx_en<=1'd0;
end
OBC_POW:begin
cmd_reg1<=cmd_reg1^8'b0000_0010;
cmd_reg <= cmd_reg1;tx_en<=1'd0;
end
DATA_POW:begin
cmd_reg2<=cmd_reg2^8'b0000_0100;
cmd_reg <= cmd_reg2;tx_en<=1'd0;
end
FIRE_POW:begin
cmd_reg3<=cmd_reg3^8'b0000_1000;
cmd_reg <= cmd_reg3;tx_en<=1'd0;
end
TRI_POW:begin
cmd_reg4<=cmd_reg4^8'b0001_0000;
cmd_reg <= cmd_reg4;tx_en<=1'd0;
end
ERROR:begin
led <= 4'b1010;
tx_en<=1'd1;
cmd_out<=8'b1111_1111;
end
WAIT:;
//tx_en <= 1'd0;
//camer_startr<=1'd0;
default: ;
endcase
assign camer_start = camer_startr;
endmodule
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