vhdl时钟冲突问题
library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity hardware_incident is
generic(Addr_type : integer:=16);
port( Hard_cs: in std_logic;
Hard_edge : in std_logic;
Hard_plus : in std_logic; --bi jiao qiao out plus zhuangtai
R_W_ctrl : in std_logic;
AddrClk: in std_logic;
AddrLine : inout std_logic_vector(0 to Addr_type-1));
end hardware_incident;
architecture beh of hardware_incident is
signal flag_num : integer;
signalflag_half : std_logic;
signal flow_write : std_logic;
signal flow_read: std_logic;
signal RAddrClk : std_logic;
signal WAddrClk : std_logic;
signalcenclk : std_logic;
signal RAddrLine: std_logic_vector(0 to Addr_type - 1);
signal WAddrLine: std_logic_vector(0 to Addr_type - 1);
signal wcenclk : std_logic;
signal rcenclk : std_logic;
signal wflag_num: integer;
signal rflag_num: integer;
BEGIN
PROCESS(R_W_ctrl,AddrClk)
BEGIN
IF(R_W_ctrl = '0')then
WAddrClk <= AddrClk;
wflag_num <= 0;
IF(WAddrClk = '1' and AddrClk = '1' and flow_write = '1')THEN
cenclk <= WAddrClk ;
IF(cenclk = '1' and WAddrClk = '1')THEN
wflag_num <= wflag_num + 1;
WAddrLine <= WAddrLine + "0000000000000001";
AddrLine <= WAddrLine ;
END IF;
IF(wflag_num = 65536)THEN
wflag_num <= 0;
WAddrLine <= "0000000000000000";
AddrLine <= WAddrLine;
END IF;
IF(wflag_num = 32767 and Hard_cs = '1' and Hard_edge = '0')THEN
wflag_num<=0 ;
flag_half <= '1';
WAddrLine <= "0111111111111111";
AddrLine <= WAddrLine;
END IF;
IF(wflag_num = 32767 and Hard_cs = '1' and Hard_edge = '1')THEN --tiao jian ju bei
wflag_num<=0 ;
flag_half <= '1';
WAddrLine <= "0111111111111111";
AddrLine <= WAddrLine;
END IF;
IF(AddrClk'event and AddrClk='1' and flag_half = '1')THEN --ying jian chu fa
wcenclk <= AddrClk ;
IF(wcenclk = '1'and AddrClk = '1' and Hard_plus = '1')THEN
wflag_num <= 0;
WAddrLine <= "0111111111111111";
AddrLine <= WAddrLine;
END IF;
END IF;
IF(wflag_num = 32767 and flag_half = '1')THEN --write half ram
wflag_num<= 0;
flag_half <= '0';
WAddrLine <= "0000000000000000";
AddrLine <= WAddrLine;
flow_read <= '1'; --read enable
END IF;
END IF;
END IF;
IF(R_W_ctrl = '1')then --read exeral enable
RAddrClk <= AddrClk;
rflag_num <= 0;
IF(RAddrClk'event and RAddrClk = '1' and flow_read = '1')THEN -- ji suan read plus ge shu
cenclk <= RAddrClk;
IF(cenclk = '1' and AddrClk = '1')THEN --add yiji wending
rflag_num <= rflag_num + 1;
rAddrLine <= RAddrLine + "0000000000000001";
AddrLine <= RAddrLine ;
END IF;
END IF;
IF(rflag_num = 65536)THEN --read plus yichu clear
rflag_num <= 0;
RAddrLine <= "0000000000000000";
AddrLine <= RAddrLine;
flow_write <= '1';
END IF;
END IF;
END PROCESS;
END beh;
烦请高手分析 问题补充: IF(RAddrClk'event and RAddrClk = '1' and flow_read = '1')THEN -- ji suan read plus ge shu
error(10818)错误
一个进程里只能有一个时钟,看一下硬件手册吧。触发器限制。多时钟拆了了,拆成多进程。 时钟语句里面又套了时钟语句, 显然是错误的. FPGA里是D触发器, 一个process只能有一个时钟.
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