分频器弄不好了，求大家帮忙，下面有代码附上
module div_mode(clk,reset,div_out,DivMode);input clk,reset;
input DivMode;
output div_out;
reg div_out;
reg N;
always @(posedge clk or negedge reset)
begin
if(!reset)
N<=12'D0;
else begin
case(DivMode)
4'b0000 :begin N<=12'd499;end//20K
4'b0001 :begin N<=12'd249;end//40K
4'b0010 :begin N<=12'd166; end//60K
4'b0011 :begin N<=12'd124; end//80K
4'b0100 :begin N<=12'd99; end//100K
4'b0101 :begin N<=12'd82; end//120K
4'b0110 :begin N<=12'd70; end//140K
4'b0111 :begin N<=12'd62; end//160K
4'B1000 :begin N<=12'd55; end//180K
4'b1001 :begin N<=12'd49; end//200K
default :begin N<=12'd499;end
endcase
end
end
reg counter1;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
counter1<=12'd0;
div_out<=1'b0;
end
elsebegin
if(counter1==N)
begin
counter1<=12'd0;
div_out<=~div_out;
end
else counter1<=counter1+1'b1;
end
end
endmodule
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