quartuseII 9.1 FFT ip核问题
我很认真的看了一下fft的user guide,但是那个是最新版的,我用的9.1版的FFT。手册上说的是最快运行速度可以到300Mhz “Maximum system clock frequency more than 300 MHz”但是我给的频率只有100MHz,但是没有输出,时序管脚控制上我觉得都没有大问题,控制器的时序仿真也没有问题。
请大神帮忙看看代码吧,谢了
我写了一个FFT的控制器,代码下面附上
module FFT_CTR(clk,rst,sw, sop, eop ,source_ready, valid ,inverse ,sink_real,sink_image);
input clk, rst, sw;
output sop,eop,source_ready,valid,inverse;
output sink_real,sink_image;
reg sop,eop,valid;
reg sink_image,realcnt;
wire sink_real;
reg state;
assign source_ready = 1;
assign inverse = 0;
assign sink_real = realcnt;
reg key_reg1,key_reg2;
always @(posedge clk or negedge rst)
if(!rst) key_reg1<=1'b1;
else key_reg1<=sw;
always @(posedge clk or negedge rst)
if(!rst) key_reg2<=1'b1;
else key_reg2<=key_reg1;
wire up = key_reg2&(~key_reg1);
//reg key_time;
//always @(posedge clk or negedge rst)
// if(!rst) key_time <= 16'h0000;
// else if(key_out)key_time <= 16'h0000;
// else key_time <= key_time + 16'h0001;
//reg low_sw;
//always @(posedge clk or negedge rst)
// if(!rst) low_sw<=1'b1;
// else if(&key_time) low_sw<= sw;
//reg low_sw_r;
//always @(posedge clk or negedge rst)
// if(!rst) low_sw_r<=1'b1;
// else low_sw_r<= low_sw;
//wire up = low_sw_r&(~low_sw);
parameter Idle=4'b0001,
Oken=4'b0010,
Start=4'b0100,
Endput=4'b1000;
always @ (posedge clk or negedge rst)
begin
if(!rst)
begin
state <= Idle;
sop <= 0;
eop <=0;
valid<=0;
//sink_real <=8'd1;
sink_image <=0;
realcnt <= 8'd1;
end
else
case(state)
Idle:
if(up)
begin
state<=Oken;
sop <= 1'b1;
valid<=1'b1;
end
else
begin
state<=Idle;
end
Oken:
begin
state <= Start;
sop <= 0;
end
Start:
begin
if(realcnt == 8'd255)
begin
state <= Endput;
eop <=1'b1;
valid <=0;
end
else
begin
realcnt <= realcnt + 8'd1;
state <= Start;
//ink_real <= realcnt;
sink_image <= 0;
end
end
Endput:
begin
state <= Idle;
eop <=0;
end
default: state<= Idle;
endcase
end
endmodule 不要沉啊,,
编译的时候有
Warning (14320): Synthesized away node "FFT:inst4|asj_fft_sglstream_fft_91:asj_fft_sglstream_fft_91_inst|auk_dspip_avalon_streaming_sink_fft_91:auk_dsp_atlantic_sink_1|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_e9h1:auto_generated|a_dpfifo_7k81:dpfifo|altsyncram_eof1:FIFOram|q_b"
这句话什么意思?
好像是说综合的时候没有综合这个部分?为什么会这个样子? 帮顶!{:smile:} 楼主,你说你的时序仿真没有问题,那source_sop上升沿之后source_real出来的是什么?可否附上图?还有,你用的是哪种数据流结构啊? ledatou 发表于 2013-8-5 22:05 static/image/common/back.gif
楼主,你说你的时序仿真没有问题,那source_sop上升沿之后source_real出来的是什么?可否附上图?还有,你 ...
source——sop我没观察过,我只注意了source_real还有source_imag,这两个值都是0,所以我觉得有问题,
其次,问我不太懂什么数据流,。刚刚入门呢。
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