求助，用VHDL语言设计一个数字钟系统（实训）
如题，虽然我对51单片机算是入门了，成功做了2辆智能小车，但我对FPGA一点都不懂；上课的时候不是逃课就是按照老师的意思抄写代码，然后调试，真不是滋味；实验箱有40多份，我还没摸过呢（老师都不给），更别说用了；求助大神们帮个忙，题目如下：2013春季学期EDA技术及应用实训任务
一、实训任务：
用VHDL语言设计一个数字钟系统
要求：
①该数字钟系统能正常显示时、分、秒；
②该数字钟系统能通过按键调整时、分；
③该数字钟系统可扩展显示日期、星期；
④该数字钟系统可设置闹钟；
二、实训目标：
1.熟练使用Quartus Ⅱ软件及VHDL语言的基本语句
2. 实践集成电路自顶向下的设计原则，理解数字系统的模块化设计
3. 在查找资料、翻阅参考书等过程中锻炼学生自主学习的能力
三、功能要求：
四、实训步骤：
1.查阅相关资料
2.参考查阅的资料，设计各功能模块
3.编写各模块的VHDL代码，并编译仿真
4.编写顶层文件，并编译仿真
5.器件编程，下载到实验箱，验证程序
5.撰写实训报告
最好有个注释（用于答辩）
实验箱芯片引脚都不知道，只知道是Cychone ii芯片 208个脚 自己先顶下 "5.器件编程，下载到实验箱，验证程序"
有目标板才知道如何显示啊
一般这样的实训 老师那都有程序{:biggrin:}
y595906642 发表于 2013-6-24 10:59 static/image/common/back.gif
"5.器件编程，下载到实验箱，验证程序"
有目标板才知道如何显示啊
一般这样的实训 老师那都有程序{:biggrin ...
问题是老师都不给实验箱，要等到程序写出来之后才给，能不能给个仿真的，引脚到时可以换；老师那里肯定有阿，他明白就跟我们说了：“连程序都给你们，这叫实训吗？”；由于在做51单片机的项目，没时间啊，感觉学FPGA很渺茫，还不如精通51来得快，下学期12月就要出去了 多练习才是王道{:lol:}
LZ加油 你们老师瞎整吧 不给试验箱
那有没有告诉你们怎么显示？
要是不负责的老师 你又没兴趣 就最后抄抄算了 y595906642 发表于 2013-6-24 12:35 static/image/common/back.gif
你们老师瞎整吧 不给试验箱
那有没有告诉你们怎么显示？
要是不负责的老师 你又没兴趣 就最后抄抄算了 ...
问题是怎么抄啊！你又不发上来 总会有人做出来的{:biggrin:}
没有实验板
不知道如何显示
程序怎么做呢？ 我不知道FPGA这么强大，拿来做电子钟！ 自己用软件看时序 写完代码 仿真看时序 时序没问题 等到看到目标板时 再分配管脚。我课程设计就是这样做出来的，全是看时序分析。不用试验箱都可以。
这种程序 实训手册后面源代码 照着敲一份就好了 不行就找同学copy一份就好了 反正大家都一样 conandllu 发表于 2013-6-24 13:37 static/image/common/back.gif
自己用软件看时序 写完代码 仿真看时序 时序没问题 等到看到目标板时 再分配管脚。我课程设计就是这样做出 ...
问题是我对VHDL语言一点都不懂啊 conandllu 发表于 2013-6-24 13:37 static/image/common/back.gif
自己用软件看时序 写完代码 仿真看时序 时序没问题 等到看到目标板时 再分配管脚。我课程设计就是这样做出 ...
可是我对Quartus ii 9.0都不太懂啊，能不能发个数字钟上来呢，只要是FPGA的数字钟 哈哈哈，李鸿明，你这小子{:biggrin:}{:biggrin:}，老师看见了。{:lol:} 小小怪 发表于 2013-6-24 22:04 static/image/common/back.gif
哈哈哈，李鸿明，你这小子，老师看见了。
什么情况？ 没有硬件外设如何写代码....... LZ，上Baidu吧，这里是amo。{:lol:} fattian8321 发表于 2013-6-25 09:59 static/image/common/back.gif
LZ，上Baidu吧，这里是amo。
大哥，百度能找得到的话，我就不在这里发帖了 深海烟花 发表于 2013-6-24 23:12 static/image/common/back.gif
没有硬件外设如何写代码.......
硬件外设已经有了：IO口随便定义，因为是用杜邦线连数码管的 有木有实例讲解，有注释的那种
难道FPGA移植就那么难吗？我看了整个论坛，都没见一个入门级的资料 数字时钟应该是FPGA入门的程序，一般课本上都有的。在看看课本吧。 中堂大人，你好！ 时钟是最简单的FPGA应用，也就是分频器+译码器，你要是看不懂《数字电路》这本书，不能用CD4000或者74LS系列搭建一个时钟的话，还是别搞FPGA了。 hitler 发表于 2013-6-26 13:14 static/image/common/back.gif
时钟是最简单的FPGA应用，也就是分频器+译码器，你要是看不懂《数字电路》这本书，不能用CD4000或者74LS系 ...
对啊，我对数字电路不熟悉，我都不想搞FPGA，也不是那的料；但要实训啊，所以求助啊
但我对单片机一见钟情的 90999 发表于 2013-6-26 13:12 static/image/common/back.gif
中堂大人，你好！
我可不是李鸿章啊 搞不了就别搞，VHDL比神马单片机难多了，完全不是一个层次的东西。 大学老师总爱拿时钟来忽悠学生，伤不起 hitler 发表于 2013-6-26 13:26 static/image/common/back.gif
搞不了就别搞，VHDL比神马单片机难多了，完全不是一个层次的东西。
我不想搞，我是被逼的；大神发个过来咧，{:handshake:} http://www.pudn.com/downloads58/sourcecode/embed/detail205103.html
我当年是拿这个链接的改的，他是用LCD显示的，你改一下，把数据输出并接到IO上控制七段译码管就好 流氓马 发表于 2013-6-26 13:30 static/image/common/back.gif
http://www.pudn.com/downloads58/sourcecode/embed/detail205103.html
我当年是拿这个链接的改的，他是用 ...
怎么下载不了，能不能发到我QQ邮箱：2495290476，谢了 LIBRARY IEEE;
USEIEEE.STD_LOGIC_1164.all;
USEIEEE.STD_LOGIC_ARITH.all;
USEIEEE.STD_LOGIC_UNSIGNED.all;
-- This code displays time in the DE2's LCD Display
-- Key2resets time
ENTITY DE2_CLOCK IS
PORT(reset, clk_50Mhz : IN STD_LOGIC;
LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED : OUT STD_LOGIC;
LCD_RW : BUFFER STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END DE2_CLOCK;
ARCHITECTURE a OF DE2_CLOCK IS
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, WRITE_CHAR1,
WRITE_CHAR2,WRITE_CHAR3,WRITE_CHAR4,WRITE_CHAR5,WRITE_CHAR6,WRITE_CHAR7,
WRITE_CHAR8, WRITE_CHAR9, WRITE_CHAR10, RETURN_HOME, TOGGLE_E, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL DATA_BUS_VALUE: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CLK_COUNT_10HZ: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL BCD_SECD0,BCD_SECD1,BCD_MIND0,BCD_MIND1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BCD_HRD0,BCD_HRD1,BCD_TSEC: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLK_400HZ, CLK_10HZ : STD_LOGIC;
BEGIN
LCD_ON <= '1';
RESET_LED <= NOT RESET;
SEC_LED <= BCD_SECD0(0);
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW = '0' ELSE "ZZZZZZZZ";
PROCESS
BEGIN
WAIT UNTIL CLK_50MHZ'EVENT AND CLK_50MHZ = '1';
IF RESET = '0' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0F424" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ <= NOT CLK_400HZ;
END IF;
END IF;
END PROCESS;
PROCESS (CLK_400HZ, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
ELSIF CLK_400HZ'EVENT AND CLK_400HZ = '1' THEN
-- GENERATE 1/10 SEC CLOCK SIGNAL FOR SECOND COUNT PROCESS
IF CLK_COUNT_10HZ < 19 THEN
CLK_COUNT_10HZ <= CLK_COUNT_10HZ + 1;
ELSE
CLK_COUNT_10HZ <= X"00";
CLK_10HZ <= NOT CLK_10HZ;
END IF;
-- SEND TIME TO LCD
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= RESET2;
WHEN RESET2 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= RESET3;
WHEN RESET3 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"08";
state <= TOGGLE_E;
next_command <= DISPLAY_CLEAR;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"01";
state <= TOGGLE_E;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"0C";
state <= TOGGLE_E;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"06";
state <= TOGGLE_E;
next_command <= WRITE_CHAR1;
-- Write ASCII hex character in first LCD character location
WHEN WRITE_CHAR1 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_HRD1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR2;
-- Write ASCII hex character in second LCD character location
WHEN WRITE_CHAR2 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_HRD0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR3;
-- Write ASCII hex character in third LCD character location
WHEN WRITE_CHAR3 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3A" ;
state <= TOGGLE_E;
next_command <= WRITE_CHAR4;
-- Write ASCII hex character in fourth LCD character location
WHEN WRITE_CHAR4 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_MIND1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR5;
-- Write ASCII hex character in fifth LCD character location
WHEN WRITE_CHAR5 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_MIND0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR6;
-- Write ASCII hex character in sixth LCD character location
WHEN WRITE_CHAR6 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3A" ;
state <= TOGGLE_E;
next_command <= WRITE_CHAR7;
-- Write ASCII hex character in seventh LCD character location
WHEN WRITE_CHAR7 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_SECD1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR8;
-- Write ASCII hex character in eighth LCD character location
WHEN WRITE_CHAR8 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_SECD0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR9;
WHEN WRITE_CHAR9 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"2E";
state <= TOGGLE_E;
next_command <= WRITE_CHAR10;
WHEN WRITE_CHAR10 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_TSEC;
state <= TOGGLE_E;
next_command <= RETURN_HOME;
-- Return write address to first character postion
WHEN RETURN_HOME =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"80";
state <= TOGGLE_E;
next_command <= WRITE_CHAR1;
-- The next two states occur at the end of each command to the LCD
-- Toggle E line - falling edge loads inst/data to LCD controller
WHEN TOGGLE_E =>
LCD_E <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END PROCESS;
PROCESS (Clk_10hz, reset)
BEGIN
IF reset = '0' THEN
BCD_HRD1 <= X"0";
BCD_HRD0 <= X"0";
BCD_MIND1 <= X"0";
BCD_MIND0 <= X"0";
BCD_SECD1 <= X"0";
BCD_SECD0 <= X"0";
BCD_TSEC<= X"0";
ELSIF clk_10HZ'EVENT AND clk_10HZ = '1' THEN
-- TENTHS OF SECONDS
IF BCD_TSEC < 9 THEN
BCD_TSEC <= BCD_TSEC + 1;
ELSE
BCD_TSEC <= X"0";
-- SECONDS
IF BCD_SECD0 < 9 THEN
BCD_SECD0 <= BCD_SECD0 + 1;
ELSE
-- TENS OF SECONDS
BCD_SECD0 <= "0000";
IF BCD_SECD1 < 5 THEN
BCD_SECD1 <= BCD_SECD1 + 1;
ELSE
-- MINUTES
BCD_SECD1 <= "0000";
IF BCD_MIND0 < 9 THEN
BCD_MIND0 <= BCD_MIND0 + 1;
ELSE
-- TENS OF MINUTES
BCD_MIND0 <= "0000";
IF BCD_MIND1 < 5 THEN
BCD_MIND1 <= BCD_MIND1 + 1;
ELSE
-- HOURS
BCD_MIND1 <= "0000";
IF BCD_HRD0 < 9 AND NOT((BCD_HRD1 = 2) AND (BCD_HRD0 = 3))THEN
BCD_HRD0 <= BCD_HRD0 + 1;
ELSE
-- TENS OF HOURS
IF NOT((BCD_HRD1 = 2) AND (BCD_HRD0 = 3)) THEN
BCD_HRD1 <= BCD_HRD1 + 1;
BCD_HRD0 <= "0000";
ELSE
-- NEW DAY
BCD_HRD1 <= "0000";
BCD_HRD0 <= "0000";
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a; 我也下载不了，但是VHDL文件可以打开看 流氓马 发表于 2013-6-26 14:04 static/image/common/back.gif
我也下载不了，但是VHDL文件可以打开看
非常感谢！我改下看看 流氓马 发表于 2013-6-26 13:30 static/image/common/back.gif
http://www.pudn.com/downloads58/sourcecode/embed/detail205103.html
我当年是拿这个链接的改的，他是用 ...
我改了，不成功啊，改得头晕转向；你不是改了吗？贴上来咧{:handshake:} 李鸿鸿 发表于 2013-6-24 22:57 static/image/common/back.gif
什么情况？
我写好了，再上传我的，虽然方法繁杂，但是，就差一个要求了 小小怪 发表于 2013-6-27 19:55 static/image/common/back.gif
我写好了，再上传我的，虽然方法繁杂，但是，就差一个要求了
是吗？明天要你的哦，我只要满足第一个要求{:handshake:} wildone 发表于 2013-6-26 13:28 static/image/common/back.gif
大学老师总爱拿时钟来忽悠学生，伤不起
这不算忽悠，能自己用VHDL设计一个时钟，这个数字电路设计算是入门了，不过撸主显然是应付差事。 我想说的是---没实体也是可以仿真的 帮顶。。。。。。。。 {:lol:}{:lol:}{:lol:}{:lol:}{:lol:}{:lol:}厉害啊啊 小小怪 发表于 2013-6-27 19:55
我写好了，再上传我的，虽然方法繁杂，但是，就差一个要求了
大神 数字钟还有吗
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