请教各位大侠关于ＣＰＬＤ的问题？ (amobbs.com 阿莫电子技术论坛) -

hhjjstu 发表于 2013-5-27 18:00:32

请教各位大侠关于ＣＰＬＤ的问题？

用verilog 写了一个代码，综合时提示：
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with

这是用xilinx ise综合时提示的错误，实际代码300多行，程序实现一个96个IO的双向控制，程序比较简单
Macrocells          Used Pterms             Registers             Used Pins Used Function Block Inputs Used
97/288(34%)    532/1440(37%)    97/288(34%)       103/168(62%)       507/576(89%)
请教一下这是什么问题？

具体程序如下：
module spi (rst,clk,
sdi,sdo,sck,cs,cmd,
port0,port1,port2,port3,port4,port5,port6,port7,port8,port9,port10,port11,
);
input    rst; // 异步清零
input    sdi; // spi data input
input    sck; // spi clk, MAX 25MHz
input    cs; // spi enable
input    clk; // cpld main clk,MIN 50MHz
input cmd;                                  // command regordat
inout port0;                // 8bit Data,configure input or outputdefault status:input
inout port1;

inout port2;
inout port3;
inout port4;
inout port5;
inout port6;
inout port7;
inout port8;
inout port9;
inout port10;
inout port11;

output reg sdo;       // spi data output
reg    receive_flag;
reg    wsdi;
reg    Bwsck;
reg    wcs;
reg    wsck;
reg    command;                               // 0:read data 1:read bit 2:write byte 3:write bit
reg status;
reg count;
reg receiver_data;
regreceiver_cmd;
reg send_buff;
regen;                                     //3态使能
reg en_bit;
reg port_reg;
reg port_bit;
regport_value;                            //端口缓存

assign port0=en? port_value:1'bz;       //默认高阻态
assign port0=en? port_value:1'bz;
assign port0=en? port_value:1'bz;
assign port0=en? port_value:1'bz;
assign port0=en? port_value:1'bz;
assign port0=en? port_value:1'bz;
assign port0=en? port_value:1'bz;
assign port0=en? port_value:1'bz;

assign port1=en ?port_value:1'bz;
assign port1=en ?port_value:1'bz;
assign port1=en?port_value:1'bz;
assign port1=en?port_value:1'bz;
assign port1=en?port_value:1'bz;
assign port1=en?port_value:1'bz;
assign port1=en?port_value:1'bz;
assign port1=en?port_value:1'bz;

assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;
assign port2=en?port_value:1'bz;

assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;
assign port3=en?port_value:1'bz;

assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;
assign port4=en?port_value:1'bz;

assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;
assign port5=en?port_value:1'bz;

assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;
assign port6=en?port_value:1'bz;

assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;
assign port7=en?port_value:1'bz;

assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;
assign port8=en?port_value:1'bz;

assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;
assign port9=en?port_value:1'bz;

assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;
assign port10=en?port_value:1'bz;

assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;
assign port11=en?port_value:1'bz;

always@(posedge clk)
begin
wsdi <= sdi;
wsck <= sck;
wcs <= cs;
   command<=cmd;
end
always@(posedge clk)
begin
Bwsck <= wsck;
end
always@(posedge clk or negedge rst or posedge wcs)
begin
if(!rst)
begin
count<=1'b0;
sdo <= 1'b0;
      en<=8'h00;
      receive_flag<=2'b00;
end
else if(wcs)
begin
sdo <= 1'b0;
count<=1'b0;
end
else if(wsck && (!Bwsck))                      //上升沿处理SPI
begin
if(command==1'b1)                                              //receive command
begin
if(count==8'h17)                                        //3byte
begin
count<=1'b0;
receiver_cmd<={receiver_cmd,wsdi};          //receiverport select
receive_flag<=1'b1;                               //receiver bit select
send_buff<=8'h00;                            //receiver read and write status control
end
else
begin
count<=count+1'b1;
receiver_cmd<={receiver_cmd,wsdi};
end
end
else if(command==1'b0)                                        //receive data
begin
if(count==4'h7)
begin
count<=1'b0;
receiver_data<=1'b0;
receiver_data <={receiver_data,wsdi};
receive_flag<=2'b10;
end
else
begin
count<=count+1'b1;
receiver_data <={receiver_data,wsdi};
end
end
end
else if(receive_flag==1'b1)                                        //command process
begin
receive_flag<=1'b0;
case(receiver_cmd)
8'h00:                                                       //read byte
begin
case(receiver_cmd)
8'h00:begin en <=8'h00; end
8'h01:begin en<=8'h00; end
8'h02:begin en<=8'h00;end
8'h03:begin en<=8'h00;end
8'h04:begin en<=8'h00;end
8'h05:begin en<=8'h00;end
8'h06:begin en<=8'h00;end
8'h07:begin en<=8'h00;end
8'h08:begin en<=8'h00;end
8'h09:begin en<=8'h00;end
8'h0a:begin en<=8'h00;end
8'h0b:begin en<=8'h00;end
endcase
status<=1'b0;
end
8'h01:                                                       //read bit
begin
case(receiver_cmd)
8'h00:begin en_bit<=8'd00; port_reg<=port0; end
8'h01:begin en_bit<=8'd08; port_reg<=port1; end
8'h02:begin en_bit<=8'd16; port_reg<=port2; end
8'h03:begin en_bit<=8'd24; port_reg<=port3; end
8'h04:begin en_bit<=8'd32; port_reg<=port4; end
8'h05:begin en_bit<=8'd40; port_reg<=port5; end
8'h06:begin en_bit<=8'd48; port_reg<=port6; end
8'h07:begin en_bit<=8'd56; port_reg<=port7; end
8'h08:begin en_bit<=8'd64; port_reg<=port8; end
8'h09:begin en_bit<=8'd72; port_reg<=port9; end
8'h0a:begin en_bit<=8'd80; port_reg<=port10;end
8'h0b:begin en_bit<=8'd88; port_reg<=port11;end
endcase
status<=1'b1;
end
8'h02:                                                       //write byte
begin
case(receiver_cmd)
8'h00:begin en <=8'hff; end
8'h01:begin en<=8'hff; end
8'h02:begin en<=8'hff;end
8'h03:begin en<=8'hff;end
8'h04:begin en<=8'hff;end
8'h05:begin en<=8'hff;end
8'h06:begin en<=8'hff;end
8'h07:begin en<=8'hff;end
8'h08:begin en<=8'hff;end
8'h09:begin en<=8'hff;end
8'h0a:begin en<=8'hff;end
8'h0b:begin en<=8'hff;end
endcase
status<=2'b10;
end
8'h03:                                                       //write_bit
begin
case(receiver_cmd)
8'h00:begin en_bit<=8'd00; port_reg<=port0; end
8'h01:begin en_bit<=8'd08; port_reg<=port1; end

8'h02:begin en_bit<=8'd16; port_reg<=port2; end
8'h03:begin en_bit<=8'd24; port_reg<=port3; end
8'h04:begin en_bit<=8'd32; port_reg<=port4; end
8'h05:begin en_bit<=8'd40; port_reg<=port5; end
8'h06:begin en_bit<=8'd48; port_reg<=port6; end
8'h07:begin en_bit<=8'd56; port_reg<=port7; end
8'h08:begin en_bit<=8'd64; port_reg<=port8; end
8'h09:begin en_bit<=8'd72; port_reg<=port9; end
8'h0a:begin en_bit<=8'd80; port_reg<=port10;end
8'h0b:begin en_bit<=8'd88; port_reg<=port11;end
endcase
status<=2'b11;
end
endcase
end
else if(receive_flag==2'b10)                                        //data process
begin
receive_flag<=1'b0;
if(status==1'b0)                                              //send byte
begin
      case(receiver_cmd)
8'h00:begin send_buff<=port0; end
8'h01:begin send_buff<=port1; end
8'h02:begin send_buff<=port2; end
8'h03:begin send_buff<=port3; end
8'h04:begin send_buff<=port4; end
8'h05:begin send_buff<=port5; end
8'h06:begin send_buff<=port6; end
8'h07:begin send_buff<=port7; end
8'h08:begin send_buff<=port8; end
8'h09:begin send_buff<=port9; end
8'h0a:begin send_buff<=port10;end
8'h0b:begin send_buff<=port11;end
endcase
status<=1'b0;
end
else if(status==1'b1)                                        //send bit
begin
case(receiver_cmd)
8'h00:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h01:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h02:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h03:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h04:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h05:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h06:begin en<=1'b0; send_buff<={send_buff,port_reg};end
8'h07:begin en<=1'b0; send_buff<={send_buff,port_reg};end
endcase
status<=1'b0;
end
else if(status==2'b10)                                        //write byte process
begin
      case(receiver_cmd)
8'h00:begin port_value<=receiver_data;end
8'h01:begin port_value <=receiver_data;end
8'h02:begin port_value<=receiver_data;end
8'h03:begin port_value<=receiver_data;end
8'h04:begin port_value<=receiver_data;end
8'h05:begin port_value<=receiver_data;end
8'h06:begin port_value<=receiver_data;end
8'h07:begin port_value<=receiver_data;end
8'h08:begin port_value<=receiver_data;end
8'h09:begin port_value<=receiver_data;end
8'h0a:begin port_value<=receiver_data;end
8'h0b:begin port_value<=receiver_data;end
endcase
status<=1'b0;
end
else if(status==2'b11)                                           //write bit process
begin
   case(receiver_cmd)
8'h00:begin port_value<=receiver_data;end
8'h01:begin port_value<=receiver_data;end
8'h02:begin port_value<=receiver_data;end
8'h03:begin port_value<=receiver_data;end
8'h04:begin port_value<=receiver_data;end
8'h05:begin port_value<=receiver_data;end
8'h06:begin port_value<=receiver_data;end
8'h07:begin port_value<=receiver_data;end
   endcase
   status<=1'b0;
end
end
else if(command==1'b0)                                              // send port data to mcu
begin
sdo<=send_buff;
end
else if(command==1'b1)
begin
sdo<=1'b0;
end
end
endmodule

jlhgold 发表于 2013-5-27 18:46:13

这句提示翻译过来就是资源不住！

642142533 发表于 2013-5-27 19:36:01

jlhgold 发表于 2013-5-27 18:46 static/image/common/back.gif
这句提示翻译过来就是资源不住！

斑竹
想你请教一下
我现在有一个jed文件，用的是XILINX的片子和ISE
怎么通过iMPACT把jed下载到CPLD中

jlhgold 发表于 2013-5-27 20:51:40

642142533 发表于 2013-5-27 19:36 static/image/common/back.gif
斑竹
想你请教一下
我现在有一个jed文件，用的是XILINX的片子和ISE

我不是吧版主我没用过xilinx

642142533 发表于 2013-5-27 21:21:45

jlhgold 发表于 2013-5-27 20:51 static/image/common/back.gif
我不是吧版主我没用过xilinx

哈哈哈，谢谢

zkf0100007 发表于 2013-5-27 21:30:57

Boundary scan ,然后右键添加 jed文件 ,然后右键 program,基本上就这样

hhjjstu 发表于 2013-5-27 22:52:33

这个问题怎么解决？

hhjjstu 发表于 2013-5-28 12:14:02

待高手来解答

yuguoliang 发表于 2013-5-31 13:51:34

642142533 发表于 2013-5-27 19:36 static/image/common/back.gif
斑竹
想你请教一下
我现在有一个jed文件，用的是XILINX的片子和ISE

注意，先把JTAG与CPLD连起来，然后给CPLD通电，再打开IMPACT，要不然你没法配置下载文件。IMPACT需要自动读取CPLD的ID然后自动配置下载参数，我估计你是卡在这里了，过了这步，在下载窗口右击加载JED文件就可以了，然后点加载进来的图标再右击选编程

hhjjstu 发表于 2013-5-31 15:03:37

看清楚的这个帖子的主题

页: [1]

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请教各位大侠关于ＣＰＬＤ的问题？