Spartan6使用DCM不能通过MAP
本帖最后由 sme 于 2013-5-22 14:41 编辑一项目，使用了XILINX FPGA，DCM做倍频用。原来使用Spartan 3S400时没有问题。
现改用Spartan6 LX45，使用ISE P&R时出错：
ERROR:Place:1355 - Component < u_clock/hf_clk_iso > is driven by DCM or PLL
component < dcm_pll48m/DCM_SP > placed at < DCM_X0Y1 >. This requires the
load component to be range constrained to CLOCKREGION_X0Y0 or
CLOCKREGION_X1Y0. Placer was not able to apply this range constraint because
component < u_clock/hf_clk_iso > has a LOC constraint or area group in a
different clock region. Please check whether the user constraints and remove
any conflicting LOCs or area groups. Note that the loads of a DCM/PLL must be
constrained to the two adjacent clock regions to the DCM/PLL.
如果删除DCM，将原来接DCM输出引脚的时钟直接连至FPGA的GCLK输入，则没有问题。
上面的提示不是很明白，似乎是要将和DCM有关的电路放限制在某块区域？
请高手指点一下，Spartan 6中使用DCM有什么注意的地方？上述问题要怎样解决？ 是不是两个DCM串联着用？ ERROR:Place:1355 - Component < u_clock/hf_clk_iso > is driven by DCM or PLL
component < dcm_pll48m/DCM_SP > placed at < DCM_X0Y1 >. This requires the
load component to be range constrained to CLOCKREGION_X0Y0 or
CLOCKREGION_X1Y0. Placer was not able to apply this range constraint because
component < u_clock/hf_clk_iso > has a LOC constraint or area group in a
different clock region. Please check whether the user constraints and remove
any conflicting LOCs or area groups. Note that the loads of a DCM/PLL must be
constrained to the two adjacent clock regions to the DCM/PLL.
两个级联的DCM要在相邻区域，你的时钟输入管脚分配已经把一个DCM（< u_clock/hf_clk_iso >）限制在一个时钟区域了；
< dcm_pll48m/DCM_SP >你是不是限制在< DCM_X0Y1 >了？ eaglefanxp 发表于 2013-5-23 10:23 static/image/common/back.gif
ERROR:Place:1355 - Component < u_clock/hf_clk_iso > is driven by DCM or PLL
component < dcm_pll48 ...
谢谢。
确实是用了两个DCM。不过我并没有人为的去分配DCM或其它任何电路放在哪个区域，我是使用synplify综合，ise只是PR，UCF文件只定义了管脚位置。
这个问题折腾了一天，现在我删了一个DCM了，才解决。{:sad:} hell-prototypes 发表于 2013-5-22 16:27 static/image/common/back.gif
是不是两个DCM串联着用？
确实是的。
提示真心看不懂，它没有提示是两个DCM带来的问题。 sme 发表于 2013-5-23 13:16 static/image/common/back.gif
确实是的。
提示真心看不懂，它没有提示是两个DCM带来的问题。
如果要串联用两个DCM，有个方法是用 Core Generator 生成 Cascading in Series with Two DCM_SP.
Core type: Cascading in Series with Two DCM_SP
Core Summary:
This Wizard allows the configuration of two instances of the Digital Clock Manager (DCM_SP) cascaded in series.
The Cascading in Series With Two DCM_SPs configuration can help produce clock frequency and phase shift which are not possible with a single DCM_SP. {:handshake:} 谢谢，记下了，下次这么干{:lol:} hell-prototypes 发表于 2013-5-22 16:27
是不是两个DCM串联着用？
我的确实是两个DCM串联使用，出的错误提示同上，请问高人有什么好的解决办法啊？
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