FIFO读写
FIFO模块 功能:ADC采集的数据,存储在FIFO中,传输给FFT模块。为了提高信噪比,将采集数据进行10次累加。即若采集1024点,将下一个采样周期过来的数据依次与前一次对应位的数据相加,重复10次。此模块在例化FIFO IP core 的基础上实现。信号:输入信号 clk_fifo FIFO 的时钟
Din 采样数据
Busy, dv, done, FFT的握手信号
输出信号:dout FIFO输出数据
Start FFT 运算开始控制
FIFO IP核
问题1 FIFO的读写时钟和采样时钟不同步,因为在WRITE0和WRITE1中分别要求读一个字节和写一个字节,所以读和写的时钟相同,但是在完成读-加-写三个时钟周期内要求采样一个数据,所以采样的时钟与读写的时钟不同步。
2FFT的时钟50M 远远快于FIFO的写时钟,要求数据快速读出,但此时FIFO的读时钟采用的和FIFO写相同时钟。
如何决定采样时钟,FIFO的读写时钟和FFT计算时钟?如何改进这个方法?
部分程序:
module FIFO_0515
#(parameter N = 12//AD resolution
)
(
input wire clk, rst,
input wire done,rfd,
input wire din,
output reg start,
output wire dout,
output wire full,empty,
output reg wr_en, rd_en,
output wire din_0
);
//reg wr_en, rd_en;
//状态声明
localparam IDLE = 4'b0001,//对FIFO初始化,写0
WRITE0 = 4'b0010,//循环写FIFO,1024*10次读1位
WRITE1 = 4'b0100,//写一位
READ = 4'b1000;//装载数据
//状态寄存器
reg current_state, next_state;
//状态控制
always @(posedge clk)
if(rst)
current_state <= IDLE;
else
current_state <= next_state;
//在初始化时向FIFO写0控制
wire sum;
assign sum = din + dout;
//wire din_0;
reg ctr;
//assign ctr = (current_state == IDLE)?0 : 1;
assign din0 = ctr ? sum : 0;
//reg count_idle;
reg count_write;
reg count_start;
//状态转移
always @*
begin
next_state = current_state;
//count_idle = 1024;
count_write=1024*10;
count_start=3;
wr_en = 0;
rd_en = 0;
start = 0;
ctr=1;
case(current_state)
IDLE:
begin
wr_en = 1;
rd_en = 0;
ctr =0 ;
if(full)
begin
next_state = WRITE0;
end
// else
// count_idle = count_idle - 1;
end
WRITE0:
begin
wr_en=0;
rd_en=1;
count_write= count_write -1;
next_state = WRITE1;
end
WRITE1:
begin
wr_en = 1;
rd_en = 0;
if(count_write == 0)
next_state = READ;
else
next_state = WRITE0;
end
READ:
begin
wr_en=0;
if(rfd)
rd_en =1;
else rd_en = 0;
if(count_start != 0)
begin
start = 1;
count_start = count_start - 1;
end
if(empty)
next_state = IDLE;
end
endcase
end
FIFO uu_fifo (
.rst(rst), // input rst
.clk(clk), // input rd_clk
.din(din_0), // input din
.wr_en(wr_en), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(dout), // output dout
.full(full), // output full
.empty(empty) // output empty
);
endmodule
我来测试下
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