警告:clk_div without an associated clock assignment 怎么解决?
如题,Warning (332060): Node: clk_div:uut_clk_div|clk_div was determined to be a clock but was found without an associated clock assignment.代码:
module clk_div
(
clk, rst_n,
clk_25MHz, sys_rst_n
);
inputclk, rst_n;
output clk_25MHz, sys_rst_n;
reg clk_div;
always @ ( posedge clk or negedge rst_n )
begin
if( !rst_n )
clk_div <= 0;
else
clk_div <= ~clk_div;
end
assign clk_25MHz = clk_div;
assign sys_rst_n = rst_n;
/****************************************/ module clk_div -----reg clk_div; 明显命名冲突了啊 denike 发表于 2013-5-15 17:04 static/image/common/back.gif
module clk_div -----reg clk_div; 明显命名冲突了啊
即使改过来也不行!有没有其他的解决方案?谢了!
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