写了一段CLC的滤波器,但是出来的波形怎么是矩形波？
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncomment the following lines to use the declarations that are
--provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hb is
Port (sysclk : in std_logic;
-- ena : in std_logic;
enclk : out std_logic;
daclk : out std_logic;
datain : in std_logic_vector(7 downto 0);
--dataine : out std_logic_vector(15 downto 0);
--sampleclk1: in std_logic; ------------------------------------------
--sampleclk1 is 10.28K
-- sampleclk2: in std_logic; ---------------------------------------------
--sampleclk2 is 10.28*256=2.63
dataout : out std_logic_vector(11 downto 0)); -------------------------------15
end hb;
architecture Behavioral of hb is
component pll is
PORT
(
areset : IN STD_LOGIC:= '0';
inclk0 : IN STD_LOGIC:= '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
---------------rclock signals is added here
----------------
signaldatainext : std_logic_vector(27 downto 0);--29
signalacca: std_logic_vector(27 downto 0);---29
signalenclk_temp: std_logic;
signaldaclk_temp: std_logic;
signal clk_50M : STD_LOGIC;
signalaccb: std_logic_vector(27 downto 0);--24
--signalaccb_delay: std_logic_vector(27 downto 0);
signalaccc: std_logic_vector(27 downto 0);
--signalaccc_delay :std_logic_vector(27 downto 0);
signalaccd: std_logic_vector(27 downto 0);
signalaccd_delay :std_logic_vector(27 downto 0);
signalcomb1: std_logic_vector(27 downto 0);--
--signalcomb1e: std_logic_vector(17 downto 0);--
signalcomb1_delay: std_logic_vector(27 downto 0);--13
signalcomb2: std_logic_vector(27 downto 0);---
signalcomb2_delay: std_logic_vector(27 downto 0);--12
signalcomb3: std_logic_vector(27 downto 0);--12
signalcomb3_delay: std_logic_vector(27 downto 0);
signalcomb4: std_logic_vector(27 downto 0);
signalcomb4_delay: std_logic_vector(27 downto 0);
signaldecimate_count: std_logic_vector(3 downto 0);
begin
--------------------produce sampleclk1 and sampleclk2
---------------------------------
-----------------rcic filter
--------------------------------
datainext(27)<=datain(7);
datainext(26)<=datain(7);
datainext(25)<=datain(7);
datainext(24)<=datain(7);
datainext(23)<=datain(7);
datainext(22)<=datain(7);
datainext(21)<=datain(7);
datainext(20)<=datain(7);
datainext(19)<=datain(7);
datainext(18)<=datain(7);
datainext(17)<=datain(7);
datainext(16)<=datain(7);
datainext(15)<=datain(7);
datainext(14)<=datain(7);
datainext(13)<=datain(7);
datainext(12)<=datain(7);
datainext(11)<=datain(7);
datainext(10)<=datain(7);
datainext(9)<=datain(7);
datainext(8)<=datain(7);
datainext(7 downto 0)<=datain(7 downto 0);
dataout<=comb4(27 downto 16);---(29 downto 14);
--enclk_temp<=sysclk;
--daclk_temp<=sysclk;
enclk <= clk_50M;
daclk <= clk_50M;
--dataine<=datain&"0000";
process (clk_50M)
begin
if clk_50M='1' and clk_50M'event then
decimate_count<=decimate_count+1;
-- if sampleclk2='1' then
acca<=acca+datainext;
-- acca_delay<=acca;
accb<=accb+acca;
accc<=accc+accb;
accd<=accd+accc;
if decimate_count="1111" then---Decimation Ratio=16
accd_delay<=accd;
comb1_delay<=comb1;
comb2_delay<=comb2;
comb3_delay<=comb3;
comb1<=accd-accd_delay;
comb2<=comb1-comb1_delay;
comb3<=comb2-comb2_delay;
comb4<=comb3-comb3_delay;
end if;
end if;
end process;
u1:pll port map (inclk0=>sysclk,c0=>clk_50M);
end Behavioral;
图。。。。。。
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