给大家分享一段最精简的1602液晶的Verilog驱动代码！
本帖最后由 hughqfb 于 2013-5-9 14:15 编辑本来是个很小的东西，由于学艺不精，耽搁了好久才理出点头绪，在此把其中的小点滴与大家分享。欢迎指导！
/*****************************************************
1602液晶显示格式：
HUMI :36.8 %
TEMP :25.5 C
*******************************************************/
module lcd1602_module(clk,reset,rs,rw,en,data,data_in);
input clk,reset;
input data_in; // 这个输入信号暂且不用
output rs,rw,en;
output data;
reg rs;
reg data;
/***************************状态转换时钟********************************/
parameter T1MS=32'd49_999;
reg count1;
reg clk_en;
always @(posedge clk or negedge reset)
if(!reset)
begin count1<=1'b0;clk_en<=1'b0;end
else if(count1==T1MS)
begin count1<=1'b0;clk_en<=~clk_en;end
else count1<=count1+1'b1;
/***************************操作液晶********************************/
reg i;
reg en_temp;
reg count2;
always @(posedge clk_en or negedge reset )
if(!reset)
begin i<=1'b0;en_temp<=1'b0;count2<=1'b0;end
else
begin
case(i)
0: begin rs<=1'b0;data<=8'h38; i<=i+1'b1; end//设置16*2显示，5*7点阵，8位数据接口
1: begin rs<=1'b0;data<=8'h0c; i<=i+1'b1; end//开显示，不显示光标，
2: begin rs<=1'b0;data<=8'h06; i<=i+1'b1; end//写入一个字符后地址指针加一且光标加一
3: begin rs<=1'b0;data<=8'h01; i<=i+1'b1; end//显示清屏
4: begin rs<=1'b0;data<=8'h80; i<=i+1'b1; end//设置第一行地址
5： begin rs<=1'b1;data<="H";i<=i+1'b1;end
6: begin rs<=1'b1;data<="U";i<=i+1'b1;end
7: begin rs<=1'b1;data<="M";i<=i+1'b1;end
8: begin rs<=1'b1;data<="I";i<=i+1'b1;end
9: begin rs<=1'b1;data<=" ";i<=i+1'b1;end
10: begin rs<=1'b1;data<=":";i<=i+1'b1;end
11: begin rs<=1'b1;data<=" ";i<=i+1'b1;end
12: begin rs<=1'b1;data<="3";i<=i+1'b1;end
13: begin rs<=1'b1;data<="6";i<=i+1'b1;end
14: begin rs<=1'b1;data<=".";i<=i+1'b1;end
15: begin rs<=1'b1;data<="8";i<=i+1'b1;end
16: begin rs<=1'b1;data<=" ";i<=i+1'b1;end
17: begin rs<=1'b1;data<="%";i<=i+1'b1;end
18: begin rs<=1'b0;data<=8'hc0; i<=i+1'b1; end // 设置第二行地址
19: begin rs<=1'b1;data<="T";i<=i+1'b1;end
20: begin rs<=1'b1;data<="E";i<=i+1'b1;end
21: begin rs<=1'b1;data<="M";i<=i+1'b1;end
22: begin rs<=1'b1;data<="P";i<=i+1'b1;end
23: begin rs<=1'b1;data<=" ";i<=i+1'b1;end
24: begin rs<=1'b1;data<=":";i<=i+1'b1;end
25: begin rs<=1'b1;data<=" ";i<=i+1'b1;end
26: begin rs<=1'b1;data<="2";i<=i+1'b1;end
27: begin rs<=1'b1;data<="5";i<=i+1'b1;end
28: begin rs<=1'b1;data<=".";i<=i+1'b1;end
29: begin rs<=1'b1;data<="5";i<=i+1'b1;end
30: begin rs<=1'b1;data<=" ";i<=i+1'b1;end
31: begin rs<=1'b1;data<="C";i<=i+1'b1;end
32: begin rs<=1'b0;data<=8'b0000_0000;i<=0;
if(count2==2'd2) // 这个地方我也不咋明白，为什么要限制写入的次数呢？
en_temp<=1'b1;
else
begin en_temp<=1'b0;count2<=count2+1'b1;end
end
default: i<=1'b0;
endcase
end
/*****************************************************************/
assign en=clk_en|en_temp;
assign rw=1'b0;
endmodule
用 C4 啊，{:victory:}牛 wkman 发表于 2013-5-9 14:24 static/image/common/back.gif
用 C4 啊，牛
这是实验室师兄的板子，我自己项目用的是C1的144Pin的。
大侠给我看下为什么需要那个count2呢？想不明白啊！ 感谢楼主分享~ 感谢分享！ 收藏了 good new! 重温verilog hughqfb 发表于 2013-5-9 15:15 static/image/common/back.gif
这是实验室师兄的板子，我自己项目用的是C1的144Pin的。
大侠给我看下为什么需要那个count2呢？想不明白 ...
这个貌似控制刷新的周期吧。。。。。。。。。。。。。 好有钱啊
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