关于vga和ps2相互连接的问题
小白一个，希望各位大神们帮忙下，将vga与ps2鼠标源码相互结合，实现左键按下彩条，右键棋盘格，中键清屏，本人实在是不懂哇 补充下，讲解也可，谢谢，本人qq 1039015116 module mouse_test(clock,left_btn,right_btn,middle_btn,wr_addr,wr_data,wr_ack,wr_req);input clock;
input left_btn;
input right_btn;
input middle_btn;
output wr_addr;
outputwr_data;
input wr_ack;
output wr_req;
reg wr_addr_r;
regwr_data_r;
regbutton_r1;
regbutton_r2;
wire button;
wire button_edge;
assign wr_data=wr_data_r;
assign wr_addr=wr_addr_r;
assign wr_req =1'b1;
always @(posedge clock)
begin
if(wr_ack)
wr_addr_r<=wr_addr_r+1'b1;
end
assign button={left_btn,middle_btn,right_btn};
always @(posedge clock)
begin
button_r1<=button;
button_r2<=button_r1;
end
assign button_edge=button_r1 & ~button_r2;
endmodule
module vga(
clock,
switch,
disp_RGB,
hsync,
vsync
);
mouse_test mouse_test(.clock(),.left_btn(left_btn),.right_btn(right_btn),
.middle_btn(middle_btn),.wr_addr(middle_btn),
.wr_data(middle_btn),.wr_ack(wr_ack),.wr_req(wr_req));
input button_edge;
input clock; //系统输入时钟 50MHz
input switch;
output disp_RGB; //VGA数据输出
output hsync; //VGA行同步信号
output vsync; //VGA场同步信号
reg hcount; //VGA行扫描计数器
reg vcount; //VGA场扫描计数器
reg data;
reg h_dat;
reg v_dat;
assignswitch=button_edge;
//reg timer;
reg flag;
wire hcount_ov;
wire vcount_ov;
wire dat_act;
wire hsync;
wire vsync;
reg vga_clk;
//VGA行、场扫描时序参数表
parameter hsync_end = 10'd95,
hdat_begin = 10'd143,
hdat_end = 10'd783,
hpixel_end = 10'd799,
vsync_end = 10'd1,
vdat_begin = 10'd34,
vdat_end = 10'd514,
vline_end = 10'd524;
always @(posedge clock)
begin
vga_clk = ~vga_clk;
end
//************************VGA驱动部分*******************************
//行扫描
always @(posedge vga_clk)
begin
if (hcount_ov)
hcount <= 10'd0;
else
hcount <= hcount + 10'd1;
end
assign hcount_ov = (hcount == hpixel_end);
//场扫描
always @(posedge vga_clk)
begin
if (hcount_ov)
begin
if (vcount_ov)
vcount <= 10'd0;
else
vcount <= vcount + 10'd1;
end
end
assign vcount_ov = (vcount == vline_end);
//数据、同步信号输
assign dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end))
&& ((vcount >= vdat_begin) && (vcount < vdat_end));
assign hsync = (hcount > hsync_end);
assign vsync = (vcount > vsync_end);
assign disp_RGB = (dat_act) ?data : 3'h00;
//************************显示数据处理部分*******************************
//图片显示延时计数器
/*always @(posedge vga_clk)
begin
flag <= vcount_ov;
if(vcount_ov && ~flag)
timer <= timer + 1'b1;
end
*/
always @(posedge vga_clk)
begin
case(switch)
3'b000: data <= h_dat; //选择横彩条
3'b100: data <= v_dat; //选择竖彩条
3'b001: data <= (v_dat ^ h_dat); //产生棋盘格
3'b010: data <= (v_dat ~^ h_dat); //产生棋盘格
endcase
end
大家帮忙看下这样有错吗？ 正在学习，还没有入门，帮不上忙了。
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