参照特权的数码管控制写的小程序 怎么搭了电路 效果不对...
`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////
// Company :
// Engineer : 特权 franchise.3
// Create Date : 2009.05.21
// Target Device: Cyclone EP1C3T144C8
// Tool versions: Quartus II 8.1
// Description : 数码管1s计数器
////////////////////////////////////////////////////////////////////////////////
module seg7(
clk,rst_n,
ds_stcp,ds_shcp,ds_data
);
input clk; //25M输入时钟信号
input rst_n; //复位信号输入，低有效
output ds_stcp; //74HC595的并行时钟输入，上升沿将当前串行输入数据并行输出
output ds_shcp; //74HC595的串行时钟输入，上升沿锁存当前串行输入数据
output ds_data; //74HC595的串行数据输入
//-------------------------------------------------
//参数定义
//数码管显示 0~9 对应段选输出
parameter SEG_NUM0 = 8'h3f,//c0,
SEG_NUM1 = 8'h06,//f9,
SEG_NUM2 = 8'h5b,//a4,
SEG_NUM3 = 8'h4f,//b0,
SEG_NUM4 = 8'h66,//99,
SEG_NUM5 = 8'h6d,//92,
SEG_NUM6 = 8'h7d,//82,
SEG_NUM7 = 8'h07,//F8,
SEG_NUM8 = 8'h7f,//80,
SEG_NUM9 = 8'h6f;//90,
//数码管位选 0~8 对应输出
parameter SEG_WE0 = 9'b111111110,
SEG_WE1 = 9'b111111101,
SEG_WE2 = 9'b111111011,
SEG_WE3 = 9'b111110111,
SEG_WE4 = 9'b111101111,
SEG_WE5 = 9'b111011111,
SEG_WE6 = 9'b110111111,
SEG_WE7 = 9'b101111111,
SEG_WE8 = 9'b011111111;
//-------------------------------------------------
//递增数据产生单元
reg cnt_1s; //1s计数器，0-49999999
reg dis_data; //数码管显示数据，36位
//1s定时计数
always @(posedge clk or negedge rst_n)
if(!rst_n) cnt_1s <= 26'd0;
else if(cnt_1s == 26'd49_999_999) cnt_1s <= 26'd0;
else cnt_1s <= cnt_1s+1'b1;
wire done_1s = (cnt_1s == 26'd49_999_999); //1s定时到标志位，高有效一个时钟周期
//显示数据每秒递增
always @(posedge clk or negedge rst_n)
if(!rst_n) dis_data <= 10'd0;
else if(done_1s) dis_data <= dis_data+1'b1;
//-------------------------------------------------
//分时显示数据控制单元
reg seg_num; //当前显示数据
reg seg_duan; //7段数码管段选信号（包括小数点为8段）
reg seg_wei; //7段数码管位选信号
reg cnt_4; //分时计数器
//分时计数器
always @(posedge clk or negedge rst_n)
if(!rst_n) cnt_4 <= 10'd0;
else cnt_4 <= cnt_4+1'b1;
//显示数据
always @(posedge clk or negedge rst_n)
if(!rst_n) seg_num <= 8'h00;
else
case(cnt_4)
4'b0000: seg_num <= dis_data;
4'b0001: seg_num <= dis_data;
4'b0010: seg_num <= dis_data;
4'b0011: seg_num <= dis_data;
4'b0100: seg_num <= dis_data;
4'b0101: seg_num <= dis_data;
4'b0110: seg_num <= dis_data;
4'b0111: seg_num <= dis_data;
4'b1000: seg_num <= dis_data;
default:seg_num <= 8'h00;
endcase
//段选数据译码
always @(posedge clk or negedge rst_n)
if(!rst_n) seg_duan <= 8'h00;
else
case(seg_num)
4'h0: seg_duan <= SEG_NUM0;
4'h1: seg_duan <= SEG_NUM1;
4'h2: seg_duan <= SEG_NUM2;
4'h3: seg_duan <= SEG_NUM3;
4'h4: seg_duan <= SEG_NUM4;
4'h5: seg_duan <= SEG_NUM5;
4'h6: seg_duan <= SEG_NUM6;
4'h7: seg_duan <= SEG_NUM7;
4'h8: seg_duan <= SEG_NUM8;
4'h9: seg_duan <= SEG_NUM9;
default: ;
endcase
//位选译码
always @(cnt_4)
case(cnt_4)
4'b0000: seg_wei <= SEG_WE0;
4'b0001: seg_wei <= SEG_WE1;
4'b0010: seg_wei <= SEG_WE2;
4'b0011: seg_wei <= SEG_WE3;
4'b0100: seg_wei <= SEG_WE4;
4'b0101: seg_wei <= SEG_WE5;
4'b0110: seg_wei <= SEG_WE6;
4'b0111: seg_wei <= SEG_WE7;
4'b1000: seg_wei <= SEG_WE8;
default:seg_wei <= 9'b111111111;
endcase
//-------------------------------------------------
//74HC95驱动译码
reg ds_stcpr; //74HC595的并行时钟输入，上升沿将当前串行输入数据并行输出
reg ds_shcpr; //74HC595的串行时钟输入，上升沿锁存当前串行输入数据
reg ds_datar; //74HC595的串行数据输入
//串行移位时钟产生
always @(posedge clk or negedge rst_n)
if(!rst_n) ds_shcpr <= 1'b0;
else if((cnt_4 > 10'h02 && cnt_4 <= 10'h22) || (cnt_4 > 10'h42 && cnt_4 <= 10'h62)
|| (cnt_4 > 10'h82 && cnt_4 <= 10'ha2) || (cnt_4 > 10'hc2 && cnt_4 <= 10'he2))
ds_shcpr <= ~ds_shcpr;
//串行移位数据产生
always @(posedge clk or negedge rst_n)
if(!rst_n) ds_datar <= 1'b0;
else
case(cnt_4)
10'h02,10'h42,10'h82,10'hc2: ds_datar <= seg_duan;
10'h04,10'h44,10'h84,10'hc4: ds_datar <= seg_duan;
10'h06,10'h46,10'h86,10'hc6: ds_datar <= seg_duan;
10'h08,10'h48,10'h88,10'hc8: ds_datar <= seg_duan;
10'h0a,10'h4a,10'h8a,10'hca: ds_datar <= seg_duan;
10'h0c,10'h4c,10'h8c,10'hcc: ds_datar <= seg_duan;
10'h0e,10'h4e,10'h8e,10'hce: ds_datar <= seg_duan;
10'h10,10'h50,10'h90,10'hd0: ds_datar <= seg_wei;
10'h12,10'h52,10'h92,10'hd2: ds_datar <= seg_wei;
10'h14,10'h54,10'h94,10'hd4: ds_datar <= seg_wei;
10'h16,10'h56,10'h96,10'hd6: ds_datar <= seg_wei;
10'h18,10'h58,10'h98,10'hd8: ds_datar <= seg_wei;
10'h1a,10'h5a,10'h9a,10'hda: ds_datar <= seg_wei;
10'h1c,10'h5c,10'h9c,10'hdc: ds_datar <= seg_wei;
10'h1e,10'h5e,10'h9e,10'hde: ds_datar <= seg_wei;
10'h20,10'h60,10'ha0,10'he0: ds_datar <= seg_wei;
default: ;
endcase
//并行移位时钟产生
always @(posedge clk or negedge rst_n)
if(!rst_n) ds_stcpr <= 1'b0;
else if((cnt_4 == 10'h02) || (cnt_4 == 10'h42) || (cnt_4 == 10'h82) || (cnt_4 == 10'hc2)) ds_stcpr <= 1'b0;
else if((cnt_4 == 10'h23) || (cnt_4 == 10'h63) || (cnt_4 == 10'ha3) || (cnt_4 == 10'he3)) ds_stcpr <= 1'b1;
wire ds_stcp = ds_stcpr;
wire ds_shcp = ds_shcpr;
wire ds_data = ds_datar;
endmodule
控制9只数码管，，程序有问题吗？
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