FPGA做异步fifo时遇到以下警告，这个怎么解决？
如题，警告如下：Warning (13004):
Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
Warning (13310): Register "wptr_full:wptr_full|wfull" is converted into an equivalent circuit using register "wptr_full:wptr_full|wfull~_emulated" and latch "wptr_full:wptr_full|wfull~latch"
Warning (13310): Register "async_cmp:async_cmp|direction" is converted into an equivalent circuit using register "async_cmp:async_cmp|direction~_emulated" and latch "async_cmp:async_cmp|direction~latch"
Warning (13310): Register "wptr_full:wptr_full|wfull2" is converted into an equivalent circuit using register "wptr_full:wptr_full|wfull2~_emulated" and latch "wptr_full:wptr_full|wfull~latch"
又遇到过的吗？？？ 代码如下：：
module wptr_full
(
wfull, wptr, afull_n,
winc, wclk, wrst_n
);
parameter ADDRSIZE = 4;
output wfull;
output wptr;
input afull_n;
input winc, wclk, wrst_n;
reg wptr, wbin;
reg wfull, wfull2;
wire wgnext, wbnext;
//---------------------------------------------------------------
// GRAYSTYLE2 pointer
//---------------------------------------------------------------
always @ ( posedge wclk or negedge wrst_n )
if( !wrst_n )
begin
wbin <= 0;
wptr <= 0;
end
else
begin
wbin <= wbnext;
wptr <= wgnext;
end
//---------------------------------------------------------------
// increment the binary count if not full
//---------------------------------------------------------------
assign wbnext = !wfull ? wbin + winc : wbin;
assign wgnext = ( wbnext >> 1 ) ^ wbnext; // binary-to-gray conversion
always @ ( posedge wclk or negedge wrst_n or negedge afull_n )
if( !wrst_n )
{wfull,wfull2} <= 2'b00;
else if( !afull_n )
{wfull,wfull2} <= 2'b11;
else
{wfull,wfull2} <= {wfull2,~afull_n};
endmodule 给wfull、wfull2等寄存器赋个初值试试 Codoox 发表于 2013-4-1 15:56 static/image/common/back.gif
给wfull、wfull2等寄存器赋个初值试试
还是不行，谢了！ always @ ( posedge wclk or negedge wrst_n or negedge afull_n )
应该是这一句的问题，FPGA中的寄存器只有一个复位端，你这用了两个，
所以编译器就Presettable and clearable registers converted to equivalent circuits with latches，
即用锁存器的方式实现，而不是寄存器。你看一下RTL图应该是生成了锁存。
不过电路的功能应该是可以实现的。 解决的办法就是：用组合逻辑先将 wrst_n和afull_n合并成一个信号，再传递到always@ Codoox 发表于 2013-4-1 16:28 static/image/common/back.gif
always @ ( posedge wclk or negedge wrst_n or negedge afull_n )
应该是这一句的问题，FPGA中的寄存器只 ...
电路功能是能实现，但是结果不可预料。我遇到过N次了，所以现在写代码很谨慎，保证生成即需要。 always @ ( posedge wclk or negedge wrst_n or negedge afull_n ) 这个写法有问题 Codoox 发表于 2013-4-1 16:32 static/image/common/back.gif
解决的办法就是：用组合逻辑先将 wrst_n和afull_n合并成一个信号，再传递到always@ ...
很感激！！！！！ orange-208 发表于 2013-4-1 22:34 static/image/common/back.gif
很感激！！！！！
不客气，互相学习{:handshake:}
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