FPGA用到同步双口RAM时出现如下警告,怎么解决?
如题,警告如下:
Warning (276027):
Inferred dual-clock RAM node "fifomem:fifomem|mem_rtl_0" from synchronous design logic.The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
有遇见过的吗??? 用系统提供的ip做双端口ram
最好不要自己写 LZ没有配置读写冲突时的输出吧
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