论坛首页 › FPGA › input clock "clk_50M" can't feed more than one pll

黄阿呆 发表于 2013-3-12 17:02:58

input clock "clk_50M" can't feed more than one pll

quartus error : input clock "clk_50M" can't feed more than one pll。是什么原因啊？

黄阿呆 发表于 2013-3-12 18:27:59

有么有那么一个人，帮我认真回答这个问

wye11083 发表于 2013-3-12 18:29:44

The Global Clock Buffer can ABSOLUTELY feed ONLY ONE PLL! You can use dedicated route constraint to force QII to use local route resources to feed your clock to another PLL which will make timing unpredictable.

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