modelsim仿真algera的fifo， 写入数据个数一直为0，为何？
modelsim仿真algera的fifo， 写入数据个数一直为0，为何？添加了 220model、altera_mf、cycloneiv_atoms、altera_primitives四个库文件 如果是库问题，modelsim会报错的，个人估计还是你代码哪里问题，你贴的图太小看不清楚，要不把代码传上来，让大家分析下。 本帖最后由 german010 于 2013-2-19 11:26 编辑
tangkuan660 发表于 2013-2-19 10:54 static/image/common/back.gif
如果是库问题，modelsim会报错的，个人估计还是你代码哪里问题，你贴的图太小看不清楚，要不把代码传上来， ...
谢谢回复， 鼠标左键点击图片，然后自动打开一个大图，可以放大看 本帖最后由 german010 于 2013-2-19 11:53 编辑
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
第一个文件testbench
`timescale 1ns/1ps
module modelsim_test_tb;
reg fpga_clk;
reg rst_n;
reg img_clk;
wire img_input_clk;
wireimg_d0;
wire img_d1;
wireimg_d2;
wireimg_d3;
wireimg_d4;`timescale 1ns/1ps
module modelsim_test_tb;
reg fpga_clk;
reg rst_n;
reg img_clk;
wire img_input_clk;
wireimg_d0;
wire img_d1;
wireimg_d2;
wireimg_d3;
wireimg_d4;
wireimg_d5;
wireimg_d6;
wireimg_d7;
regimg_d_en;
regimg_Xsync;
wire img_lr_sel;
wire img_line_sp_100Hz;
reg img_ir_sensor;
wire rs232_tx;
regrs232_rx;
wire img_state0;
wire img_state1;
wire img_state_trg;
wire img_spi_sclk;
wire img_spi_en;
wire img_spi_mosi;
wire clk_100m;
//==============================================================================================
parameter CLOCK_40NS = 40;
initial
begin
fpga_clk = 1'b0;
forever
# (CLOCK_40NS/2) fpga_clk = ~fpga_clk; // 25MHz CLOCK
end
//------------------------------------------------------------------
parameter RESET_TIME = 200;
initial
begin
rst_n = 1'b0; // RESET pulse
#RESET_TIME rst_n = 1'b1;
// #RESET_TIME rst_n = 1'b1; //after 1us,RESET over
end
//===============================================================================================data gene
//data clk
parameter CLOCK_56ns = 56;
always @(posedge img_line_sp_100Hz)
begin
img_clk = 1'b0;
repeat(3800) # (CLOCK_56ns/2) img_clk = ~img_clk; // 18MHz CLOCK
end
always @(posedge img_line_sp_100Hz)//-----------------------------------------------img_d_en
begin
img_d_en <= 1'b1;
#(CLOCK_56ns*317 ) img_d_en <= 1'b0;
end
always @(posedge img_line_sp_100Hz)//-----------------------------------------------img_d_en
#(CLOCK_56ns*1900) img_d_en <= 1'b1;
always @(posedge img_line_sp_100Hz)
begin
//-----------------------------------------------Xsync
img_Xsync <= 1'b0;
#(CLOCK_56ns*150 ) img_Xsync <= 1'b1;
#CLOCK_56ns img_Xsync <= 1'b0;
end
//-----------------------------------------------img_input_clk for data generation,not for the input of sdr_test
assign img_input_clk = img_clk & !img_d_en;
//-------------------------------------------------------------------------------------------------data input
reg flg_r;
reg send_data_r;
always@(negedge img_input_clk or negedge rst_n)
if(!rst_n)
send_data_r <= 8'd0;
else
send_data_r <=send_data_r+8'd1;
assign {img_d7,img_d6,img_d5,img_d4,img_d3,img_d2,img_d1,img_d0}= send_data_r;
// img_fifo_input_clk
//------------------------------------------------------------------------------------------------img data task
//==============================================================================================spi ctrl
parameterBPS_115200 = 8681;//8681?115200????
parameterDELAY_TIME= 200;
integer i;
reg test_data_232;
initial
begin
rs232_rx = 1'b1;
#DELAY_TIME test_data_232 = 16'h72;
transmit_data_232(test_data_232);
# (BPS_115200*15);//delay 1 unit transmit time
test_data_232 = 16'h02;
transmit_data_232(test_data_232);
# (BPS_115200*15);//delay 1 unit transmit time
end
//----------------------------rcv data task
task transmit_data_232;
input SEND_DATA_232;
begin
rs232_rx = 1'b1; //RESET rs232_rx
# BPS_115200 rs232_rx = 1'b0; // transmit START bit
$display ("write data: %x\n",SEND_DATA_232);
for(i=0;i<8;i=i+1) //transmit DATA byte
# BPS_115200 rs232_rx = SEND_DATA_232;
# BPS_115200 rs232_rx = 1'b0; // transmit STOP bit
# BPS_115200 rs232_rx = 1'b1; // bus IDLE
end
endtask
//===============================================================================================instance
sdr_test sdr_test(
//data in
.fpga_clk(fpga_clk),
.key3_rst_n(rst_n),//key1
//
//.img_fifo_input_clk(img_fifo_input_clk),//output signal for verification
.img_clk(img_clk), //scope of img_clk is bigger than img_input_clk
.img_d0(img_d0),
.img_d1(img_d1),
.img_d2(img_d2),
.img_d3(img_d3),
.img_d4(img_d4),
.img_d5(img_d5),
.img_d6(img_d6),
.img_d7(img_d7),
.img_d_en(img_d_en),//
.img_Xsync(img_Xsync),
.img_lr_sel(img_lr_sel),
.img_line_sp_100Hz(img_line_sp_100Hz),
.img_ir_sensor(img_ir_sensor),
//rs232
.rs232_tx(rs232_tx),
.rs232_rx(rs232_rx),
/*
sdram_clk(),
sdram_cke(),
sdram_cs_n(),
sdram_ras_n(),
sdram_cas_n(),
sdram_we_n(),
sdram_ba(),
sdram_addr(),
sdram_udqm(),
sdram_ldqm(),
sdram_data(),
*/
//state change
.img_state0(img_state0),
.img_state1(img_state1),
.img_state_trg(img_state_trg),
//serial command
.img_spi_sclk(img_spi_sclk),
.img_spi_en(img_spi_en),
.img_spi_mosi(img_spi_mosi),
//test command
//.test_sig1(test_sig1),
//.test_sig2(test_sig2),
//.test_flg3(test_flg3),
// cmd_coming_sig
.clk_100m(clk_100m)
);
endmodule
wireimg_d5;
wireimg_d6;
wireimg_d7;
regimg_d_en;
regimg_Xsync;
wire img_lr_sel;
wire img_line_sp_100Hz;
reg img_ir_sensor;
wire rs232_tx;
regrs232_rx;
wire img_state0;
wire img_state1;
wire img_state_trg;
wire img_spi_sclk;
wire img_spi_en;
wire img_spi_mosi;
wire clk_100m;
//==============================================================================================
parameter CLOCK_40NS = 40;
initial
begin
fpga_clk = 1'b0;
forever
# (CLOCK_40NS/2) fpga_clk = ~fpga_clk; // 25MHz CLOCK
end
//------------------------------------------------------------------
parameter RESET_TIME = 200;
initial
begin
rst_n = 1'b0; // RESET pulse
#RESET_TIME rst_n = 1'b1;
// #RESET_TIME rst_n = 1'b1; //after 1us,RESET over
end
//===============================================================================================data gene
//data clk
parameter CLOCK_56ns = 56;
always @(posedge img_line_sp_100Hz)
begin
img_clk = 1'b0;
repeat(3800) # (CLOCK_56ns/2) img_clk = ~img_clk; // 18MHz CLOCK
end
always @(posedge img_line_sp_100Hz)//-----------------------------------------------img_d_en
begin
img_d_en <= 1'b1;
#(CLOCK_56ns*317 ) img_d_en <= 1'b0;
end
always @(posedge img_line_sp_100Hz)//-----------------------------------------------img_d_en
#(CLOCK_56ns*1900) img_d_en <= 1'b1;
always @(posedge img_line_sp_100Hz)
begin
//-----------------------------------------------Xsync
img_Xsync <= 1'b0;
#(CLOCK_56ns*150 ) img_Xsync <= 1'b1;
#CLOCK_56ns img_Xsync <= 1'b0;
end
//-----------------------------------------------img_input_clk for data generation,not for the input of sdr_test
assign img_input_clk = img_clk & !img_d_en;
//-------------------------------------------------------------------------------------------------data input
reg flg_r;
reg send_data_r;
always@(negedge img_input_clk or negedge rst_n)
if(!rst_n)
send_data_r <= 8'd0;
else
send_data_r <=send_data_r+8'd1;
assign {img_d7,img_d6,img_d5,img_d4,img_d3,img_d2,img_d1,img_d0}= send_data_r;
// img_fifo_input_clk
//------------------------------------------------------------------------------------------------img data task
//==============================================================================================spi ctrl
parameterBPS_115200 = 8681;//8681?115200????
parameterDELAY_TIME= 200;
integer i;
reg test_data_232;
initial
begin
rs232_rx = 1'b1;
#DELAY_TIME test_data_232 = 16'h72;
transmit_data_232(test_data_232);
# (BPS_115200*15);//delay 1 unit transmit time
test_data_232 = 16'h02;
transmit_data_232(test_data_232);
# (BPS_115200*15);//delay 1 unit transmit time
end
//----------------------------rcv data task
task transmit_data_232;
input SEND_DATA_232;
begin
rs232_rx = 1'b1; //RESET rs232_rx
# BPS_115200 rs232_rx = 1'b0; // transmit START bit
$display ("write data: %x\n",SEND_DATA_232);
for(i=0;i<8;i=i+1) //transmit DATA byte
# BPS_115200 rs232_rx = SEND_DATA_232;
# BPS_115200 rs232_rx = 1'b0; // transmit STOP bit
# BPS_115200 rs232_rx = 1'b1; // bus IDLE
end
endtask
//===============================================================================================instance
sdr_test sdr_test(
//data in
.fpga_clk(fpga_clk),
.key3_rst_n(rst_n),//key1
//
//.img_fifo_input_clk(img_fifo_input_clk),//output signal for verification
.img_clk(img_clk), //scope of img_clk is bigger than img_input_clk
.img_d0(img_d0),
.img_d1(img_d1),
.img_d2(img_d2),
.img_d3(img_d3),
.img_d4(img_d4),
.img_d5(img_d5),
.img_d6(img_d6),
.img_d7(img_d7),
.img_d_en(img_d_en),//
.img_Xsync(img_Xsync),
.img_lr_sel(img_lr_sel),
.img_line_sp_100Hz(img_line_sp_100Hz),
.img_ir_sensor(img_ir_sensor),
//rs232
.rs232_tx(rs232_tx),
.rs232_rx(rs232_rx),
/*
sdram_clk(),
sdram_cke(),
sdram_cs_n(),
sdram_ras_n(),
sdram_cas_n(),
sdram_we_n(),
sdram_ba(),
sdram_addr(),
sdram_udqm(),
sdram_ldqm(),
sdram_data(),
*/
//state change
.img_state0(img_state0),
.img_state1(img_state1),
.img_state_trg(img_state_trg),
//serial command
.img_spi_sclk(img_spi_sclk),
.img_spi_en(img_spi_en),
.img_spi_mosi(img_spi_mosi),
//test command
//.test_sig1(test_sig1),
//.test_sig2(test_sig2),
//.test_flg3(test_flg3),
// cmd_coming_sig
.clk_100m(clk_100m)
);
endmodule
/////////////////////////////////////////////////////////////////////////////////////////
第二个文件 top model
`timescale 1ns / 1ps
module sdr_test(
//data in
fpga_clk,
key3_rst_n,//key1
//
// img_fifo_input_clk,
img_clk,
img_d0,
img_d1,
img_d2,
img_d3,
img_d4,
img_d5,
img_d6,
img_d7,
img_d_en,
img_Xsync,
img_lr_sel,
img_line_sp_100Hz,
img_ir_sensor,
//rs232
rs232_tx,
rs232_rx,
/*
sdram_clk,
sdram_cke,
sdram_cs_n,
sdram_ras_n,
sdram_cas_n,
sdram_we_n,
sdram_ba,
sdram_addr,
sdram_udqm,
sdram_ldqm,
sdram_data,
*/
//state change
img_state0,
img_state1,
img_state_trg,
//serial command
img_spi_sclk,
img_spi_en,
img_spi_mosi,
//test command
test_sig1,
test_sig2,
test_flg3,
// cmd_coming_sig
clk_100m
);
//================================================================
input fpga_clk; //ç³»ç»æ¶éï¼25MHz
//ç³»ç»æ§å¶ç¸å ³ä¿¡å·æ¥å£
wire clk_25m; //PLLè¾åº25MHzæ¶é
output clk_100m; //PLLè¾åº100MHzæ¶é
//wire clk_18m;
//ä¾åç³»ç»å¤ä½ä¿¡å·åPLLæ§å¶æ¨¡å=======================================
input key3_rst_n;
output img_line_sp_100Hz;
wire clk_1m;
sys_ctrl uut_sysctrl(
.clk(fpga_clk),
.rst_n(key3_rst_n),
.clk_25m(clk_25m),
.clk_1m(clk_1m),
.clk_100m(clk_100m),
.sdram_clk(sdram_clk)
);
//------------------------------------------------
input img_clk;
input img_d0;
input img_d1;
input img_d2;
input img_d3;
input img_d4;
input img_d5;
input img_d6;
input img_d7;
input img_d_en;
input img_Xsync;
output img_lr_sel;
wire img_wrf_wrreq;
wire line_ch_flg;
wire get_one_data_flg;
wireimg_wrf_din;
datagene datagene_inst(
//input
.img_clk(img_clk),
.rst_n(key3_rst_n),
.img_d0(img_d0),
.img_d1(img_d1),
.img_d2(img_d2),
.img_d3(img_d3),
.img_d4(img_d4),
.img_d5(img_d5),
.img_d6(img_d6),
.img_d7(img_d7),
.img_d_en(img_d_en),
.Xsync(img_Xsync),
//
.wrf_din(img_wrf_din),
.wrf_wrreq(img_wrf_wrreq),
//
.line_ch_flg(line_ch_flg),
.get_one_data_flg(get_one_data_flg)
);
assign img_lr_sel = 1'b1;
//ä¾å串å£æ°æ®åéæ§å¶æ¨¡å
//------------------------------------------------
//======================================================================================================
wire img_fifo_input_clk;//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//wireclk_25m;
wire img_rdf_rdreq;
wire img_rdf_dout;
//-------------------------------------
wire img_wrusedw_sig;
wire img_wrempty_sig;
wire img_wrfull_sig;
wire img_rdusedw_sig;
wire img_rdempty_sig;
wire img_rdfull_sig ;
//img fifo output
wire img_fifo_o_clk;
wire img_fifo_o_data;
wire img_fifo_o_rdy;
wire img_fifo_o_req;
// uart fifo output
wire uart_fifo_o_data;
wire uart_fifo_o_rdy;
wire uart_fifo_o_req;
wire uart_fifo_tx_start;
wireneg_wrack;
wire sys_data_out; //sdramæ°æ®è¯»åºç¼åFIFOè¾å ¥æ°æ®æ»çº¿
wire tx_data; //å¾ åéæ°æ®
wire tx_start;
wire rdreq_t;
assign img_fifo_input_clk =img_clk && ~img_d_en;
fifo_ctrlfifo_ctrl_inst(
.rst_n (key3_rst_n),
.img_clk (img_fifo_input_clk),
.img_wrf_wrreq (img_wrf_wrreq),
.img_wrf_din (img_wrf_din),
.clk_100m (clk_25m),
.img_rdf_rdreq (rdreq_t),
.img_rdf_dout (tx_data),
.sdram_wr_req (tx_start), //---------------------------------
//--------------------------------------
.uart_wr_clk(clk_100m),
.uart_wrreq(neg_rdack),
.uart_wr_data(sys_data_out),
.sdram_rd_req(),
//
.uart_rdclk(clk_25m),
.uart_rdreq(uart_fifo_o_req),
.uart_q (uart_fifo_o_data),
.uart_fifo_tx_start(uart_fifo_tx_start)
);
//ä¾å模æåå ¥æ°æ®å°sdram模å====================================
wiremoni_addr;
wireaddr_rd_flg;
//ä¾åSDRAMå°è£ æ§å¶æ¨¡å=======================================
// SDRAMçå°è£ æ¥å£
wire sdram_wr_req; //ç³»ç»åSDRAM请æ±ä¿¡å·
wire sdram_rd_req; //ç³»ç»è¯»SDRAM请æ±ä¿¡å·
wire sdram_wr_ack; //ç³»ç»åSDRAMååºä¿¡å·,ä½ä¸ºwrFIFOçè¾åºææä¿¡å·
wire sdram_rd_ack; //ç³»ç»è¯»SDRAMååºä¿¡å·,ä½ä¸ºrdFIFOçè¾åææä¿¡å·
//wire sys_addr; //读åSDRAMæ¶å°åæåå¨ï¼(bit21-20)L-Bankå°å:(bit19-8)为è¡å°åï¼(bit7-0)为åå°å
wire sys_data_in; //åSDRAMæ¶æ°æ®æåå¨
wire sdram_busy; // SDRAMå¿æ å¿ï¼é«è¡¨ç¤ºSDRAMå¤äºå·¥ä½ä¸
wire sys_dout_rdy; // SDRAMæ°æ®è¾åºå®ææ å¿
//=======================================================
wire rtn;
output img_state0;
output img_state1;
output img_state_trg;
output img_spi_sclk;
output img_spi_en;
output img_spi_mosi;
inputimg_ir_sensor;
//------------------------------------------------
output test_sig1;
output test_sig2;
//cmd ctrl interface
wirecmd_coming_sig;
wirerd_cmd_sig;
//uart output interface
//232 interface
output rs232_tx;
inputrs232_rx;
wire rx_data;
//----------------------------------------------------
uart_ctrl uart_ctrl(
.key3_rst_n(key3_rst_n),
.clk_25m(clk_25m),
.clk_1m(clk_1m),
.clk_100m(clk_100m),
//cmd ctrl interface-----------------------------
.rx_data(rx_data),
//data output interface-------------------------
.tx_data(tx_data), //å¾ åéæ°æ®
.tx_start(tx_start),
.rdreq_t(rdreq_t),
//232 interface--------------------------------
.rs232_tx(rs232_tx),
.rs232_rx(rs232_rx),
.test_flg3(test_flg3),
//spi-------------------------------------------
.sclk(img_spi_sclk),
.csb(img_spi_en),
.mosi(img_spi_mosi),
//state change----------------------------------
.state0(img_state0),
.state1(img_state1),
.state_trg(img_state_trg),
//data out ---------------------------------------
.line_sp(img_line_sp_100Hz),
.beginflg(beginflg),
.ir_sensor(img_ir_sensor),
.line_ch_flg(line_ch_flg),
.get_one_data_flg(get_one_data_flg)
);
//
output test_flg3;
//change the line
//output interface
/*
img_fifo_o_clk
img_fifo_o_req
img_fifo_o_data
img_fifo_o_rdy
uart_fifo_o_clk
uart_fifo_o_req
uart_fifo_o_data
uart_fifo_o_rdy
*/
//img_fifo interface
/*
assign img_fifo_o_req = (line_ch_flg == 1'b1) ? sdram_wr_ack :rdreq_t;
assign sys_data_in = (line_ch_flg == 1'b1) ? img_fifo_o_data :1'b0 ;
assign img_fifo_o_clk = (line_ch_flg == 1'b1) ? clk_100m :clk_25m;
assign tx_data = (line_ch_flg == 1'b1) ? uart_fifo_o_data :img_fifo_o_data;
assign tx_start = (line_ch_flg == 1'b1) ? uart_fifo_tx_start :img_fifo_o_rdy;
assign sdram_wr_req = (line_ch_flg == 1'b1) ? img_fifo_o_rdy :1'b0 ;
assign uart_fifo_o_req= (line_ch_flg == 1'b1) ? rdreq_t :1'b0 ;
*/
/*
assign img_fifo_o_req = rdreq_t;
assign sys_data_in = 1'b0 ;
assign img_fifo_o_clk = clk_25m;
assign tx_data = img_fifo_o_data;
assign tx_start = img_fifo_o_rdy ;
assign sdram_wr_req = 1'b0 ;
assign uart_fifo_o_req= 1'b0 ;
*/
//sdram interface
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
第三个文件 fifo 控制
`timescale 1ns / 1ps
modulefifo_ctrl(
rst_n,
img_clk,
img_wrf_wrreq,
img_wrf_din,
clk_100m,
img_rdf_rdreq,
img_rdf_dout,
sdram_wr_req,
//-------------------------------------------
uart_wr_clk,
uart_wrreq,
uart_wr_data,
sdram_rd_req,
uart_rdclk,
uart_rdreq,
uart_q,
uart_fifo_tx_start
);
//======================================================
inputrst_n;
inputimg_clk;
inputimg_wrf_wrreq;
inputimg_wrf_din;
inputclk_100m;
inputimg_rdf_rdreq;
output img_rdf_dout;
wire img_rdempty_sig ;
wire img_rdfull_sig ;
wire img_rdusedw_sig;
wire img_wrempty_sig ;
wire img_wrfull_sig ;
wire img_wrusedw_sig;
reg aclr_sig_r;
wire aclr_sig;
//output tx_start;
outputsdram_wr_req;
reg sdram_wr_reqr;
always @(posedge clk_100m)
if(img_rdempty_sig ==1'b0)
sdram_wr_reqr <=1'b1; //å¯å¨ åéæ°æ®;
else
sdram_wr_reqr <=1'b0;
assign sdram_wr_req=sdram_wr_reqr ;
imgfifo imgfifo_inst (
.wrclk( img_clk ),
.wrreq( img_wrf_wrreq ),
.data ( img_wrf_din ),
.rdclk( clk_100m ),
.rdreq( img_rdf_rdreq ),
.q ( img_rdf_dout),
.rdempty(img_rdempty_sig ),
.rdfull (img_rdfull_sig),
.rdusedw(img_rdusedw_sig ),
.wrempty(img_wrempty_sig ),
.wrfull (img_wrfull_sig),
.wrusedw(img_wrusedw_sig ),//????????????????????????????????
.aclr ( aclr_sig_r )
);
//=====================================================================================================================================
inputuart_wr_clk;
inputuart_wrreq;
inputuart_wr_data;
inputuart_rdclk;
inputuart_rdreq;
output uart_q;
wire uart_rdempty;
wire uart_rdfull;
wire uart_rdusedw;//..................................
wire uart_wrempty;
wire uart_wrfull;
wire uart_wrusedw;
reguart_aclr_sigr;//read side
output sdram_rd_req;
reg sdram_rd_reqr;
always @(posedge uart_rdclk )
if(uart_rdempty == 1'b1&& sdram_wr_reqr == 1'b0)
sdram_rd_reqr <= 1'b1;
else if(uart_wrusedw >= 9'd256)
sdram_rd_reqr <= 1'b0;
assign sdram_rd_req = sdram_rd_reqr ;//& syswr_done;
//uart rd ctrl
output uart_fifo_tx_start;
assign uart_fifo_tx_start = ~uart_rdempty;
//output for request uart
/*
uartfifo uartfifo_inst (
.wrclk( uart_wr_clk ),
.wrreq( uart_wrreq),
.data ( uart_wr_data),
.rdclk( uart_rdclk),
.rdreq( uart_rdreq),
.q ( uart_q ),
.rdempty(uart_rdempty ),
.rdfull (uart_rdfull),
.rdusedw(uart_rdusedw ),
.wrempty(uart_wrempty ),
.wrfull (uart_wrfull),
.wrusedw(uart_wrusedw ),
.aclr (uart_aclr_sigr)
);
*/
endmodule
///////////////////////////////////////////////////////////////////////////////////
第四个文件，添加fifo的时候 quartus ii 自动生成的fifo代码
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: imgfifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors.Please refer to the
//applicable agreement for further details.
// synopsys translate_off
// synopsys translate_on
`timescale 1 ps / 1 ps
module imgfifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output q;
output rdempty;
output rdfull;
output rdusedw;
output wrempty;
output wrfull;
output wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wiresub_wire0;
wiresub_wire1;
wire sub_wire2;
wiresub_wire3;
wiresub_wire4;
wire sub_wire5;
wire sub_wire6;
wirewrempty = sub_wire0;
wirewrfull = sub_wire1;
wire q = sub_wire2;
wirerdempty = sub_wire3;
wirerdfull = sub_wire4;
wire wrusedw = sub_wire5;
wire rdusedw = sub_wire6;
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrclk (wrclk),
.wrempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2),
.rdempty (sub_wire3),
.rdfull (sub_wire4),
.wrusedw (sub_wire5),
.rdusedw (sub_wire6)
);
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 2048,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 3,
dcfifo_component.read_aclr_synch = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL "rdusedw"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL imgfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL imgfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL imgfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL imgfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL imgfifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL imgfifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf 我放大看了，你调用的是altera的哪个FIFO库啊？应该不是所有FIFO实例的信号吧？能不把所有FIFO接口信号都贴出来？ tangkuan660 发表于 2013-2-19 11:32 static/image/common/back.gif
我放大看了，你调用的是altera的哪个FIFO库啊？应该不是所有FIFO实例的信号吧？能不把所有FIFO接口信号都贴 ...
最后的 第四个文件里 有所有fifo的 信号 看了下你贴的代码，应该是.aclr (uart_aclr_sigr)这个信号你没有赋值，这是FIFO的异步复位信号，高电平FIFO就是复位状态，正确的连接到你的全局复位信号上看看，注意复位电平哦。 tangkuan660 发表于 2013-2-19 11:38 static/image/common/back.gif
看了下你贴的代码，应该是.aclr (uart_aclr_sigr)这个信号你没有赋值，这是FIFO的异步复位信号，高电平 ...
哦，谢谢，我看下
我之所以用modelsim仿真代码，是因为原来的代码在实际的fpga上运行 只能产生部分效果，但毛病我找到了，不在这里，
但用modelsim，这里找出了问题，感觉 modelsim对代码的要求比实际fpga硬件还严格！？
可以说明一下到底是哪里有问题吗？我也遇上同样的问题，写入的个数一直是1，不知道怎么解决，我是个新手，请各位大神帮帮忙。。
我的是aclr 信号的问题
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