xilinx SIE仿真问题
按照一本书练习vhdl语言，仿真时遇到了问题，ise10.1版本，请教各位前辈，这是什么问题？错误提示:ERROR:Simulator:29 - at 0 ns : Delay 50000000 fs is not greater than previous waveform element delay 500000000 fs in assignment for target signal load
仿真语句：
ENTITY MY_CNTR_TB IS
END MY_CNTR_TB;
ARCHITECTURE behavior OF MY_CNTR_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MY_CNTR
PORT(
CLK : INstd_logic;
RST : INstd_logic;
D_IN : INstd_logic_vector(7 downto 0);
Q_OUT : OUTstd_logic_vector(7 downto 0);
LOAD : INstd_logic;
CE : INstd_logic;
UPDN : INstd_logic
);
END COMPONENT;
--Inputs
signal CLK_SIG : std_logic := '0';
signal RST : std_logic := '1';
signal D_IN : std_logic_vector(7 downto 0) := X"0F";
signal LOAD : std_logic := '0';
signal CE : std_logic := '1';
signal UPDN : std_logic := '1';
--Outputs
signal Q_OUT : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MY_CNTR PORT MAP (
CLK => CLK_SIG,
RST => RST,
D_IN => D_IN,
Q_OUT => Q_OUT,
LOAD => LOAD,
CE => CE,
UPDN => UPDN
);
CLK_SIG <= not CLK_SIG after 5 ns;
-- Stimulus process
stim_proc: process
begin
CE <= '1','0' after 300 ns,'1' after 400 ns;
RST <= '0' after 15 ns,'1' after 40 ns;
UPDN <= '0' after 750 ns;
LOAD <= '1' after 500 ns, '0' after 50 ns;
wait;
end process;
END; 可以把源码也上传上来，我试试仿真帮你看看，只看test_bech，也看不出来
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