[请教]:FPGA从视频656数据流中提取奇/偶场的起始位置.
[请教]:FPGA从视频656数据流中提取奇/偶场的起始位置.小弟不才,还在慢慢摸索中;
目的想实现: 从视频656数据流中找到FF 00 00 80/C7,然后再找到FF 00 00 C7/80, 这样就可以找到了某场的 StartOfOddFieldFlag标志;
大侠们帮忙看看下面代码. 部分代码从zrtech资料中的来的. 谢谢了
module receiver(
rst_n,
qd,
clk,
qfv,
qfv_odd,
qfv_even,
StartOfOddFieldFlag,
qd_out
);
// ports
input rst_n;
input qd;
input clk;
output qfv,qfv_odd,qfv_even;
outputStartOfOddFieldFlag;// =1'b1
outputqd_out;
//internal
reg qd_dly,qd_dly1,qd_dly2,qd_dly3;
assign qd_out = (StartOfOddFieldFlag)? qd_dly3 : 8'hab;
always @ (posedge clk) begin
qd_dly<= qd;
qd_dly1 <= qd_dly;
qd_dly2 <= qd_dly1;
qd_dly3 <= qd_dly2;
end
reg ODD_STATE;
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin
ODD_STATE <= 0;
end
else
case(ODD_STATE) //FF 000080
3'd0: if(qd_dly==8'hff)
ODD_STATE <= 3'd1;
else
ODD_STATE <= 3'd0;
3'd1: if(qd_dly==8'h00)
ODD_STATE <= 3'd2;
else if(qd_dly==8'hff)
ODD_STATE <= 3'd1;
else
ODD_STATE <= 3'd0;
3'd2: if(qd_dly==8'h00)
ODD_STATE <= 3'd3;
else
ODD_STATE <= 3'd0;
3'd3: if(qd_dly==8'h80) //qfv_odd
ODD_STATE <= 3'd4;
else if(qd_dly==8'h9d)
ODD_STATE <= 3'd5;
else if(qd_dly == 8'hc7) //qfv_even
ODD_STATE <= 3'd6;
else if(qd_dly == 8'hda)
ODD_STATE <= 3'd7;
else
ODD_STATE <= 3'd0;
3'd4: ODD_STATE <= 1'b0;
3'd5: ODD_STATE <= 1'b0;
3'd6: ODD_STATE <= 1'b0;
3'd7: ODD_STATE <= 1'b0;
endcase
wire qfv = qfv_even | qfv_odd;
reg qfv_cnt;
always @ (posedge clk or negedge rst_n)
if(!rst_n)
qfv_cnt <= 1'b0;
else if(qfv)
qfv_cnt <= qfv_cnt + 1'b1;
else
qfv_cnt <= 1'b0;
reg qfv_odd;
always @ (posedge clk or negedge rst_n)
if(!rst_n)
qfv_odd <= 1'b0;
else if(ODD_STATE == 3'd4) // one frame
qfv_odd <= 1'b1;
else if(qfv_cnt == 11'd1439)
qfv_odd <= 1'b0;
reg qfv_even;
always @ (posedge clk or negedge rst_n)
if(!rst_n)
qfv_even <= 1'b0;
else if(ODD_STATE == 3'd6)
qfv_even <= 1'b1;
else if(qfv_cnt == 11'd1439)
qfv_even <= 1'b0;
//find 1st(odd frame) line of odd field,when state=3.
reg STATE;
reg StartOfOddFieldFlag;
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin
STATE <= 1'b0;
StartOfOddFieldFlag <=1'b0;
end
else
case(STATE)
3'd0: if(qfv_even) begin //find the first line of odd frame.
STATE <= 3'd1;
StartOfOddFieldFlag <=1'b0;
end
else begin
STATE <= 3'd0;
StartOfOddFieldFlag <=1'b0;
end
3'd1: if(qfv_odd) begin
STATE <= 3'd2;
StartOfOddFieldFlag <=1'b1;
end
else
STATE <= 3'd1;
3'd2: if(qfv_odd | qfv_even) //qfv_dly <= qfv_odd | qfv_even; ==find actvie pixel area per line,
STATE <= 3'd3; //to aviod the blanking(eav+280+sav) per line.
else
STATE <= 3'd2;
3'd3: if(!(qfv_odd | qfv_even))
STATE <= 3'd4;
else
STATE <= 3'd3;
3'd4: STATE <= 3'd2;
endcase
endmodule 代码比较繁琐、BT656行场信号解织10来行代码就够的、 蓝色风暴@FPGA 发表于 2013-1-16 17:35 static/image/common/back.gif
代码比较繁琐、BT656行场信号解织10来行代码就够的、
可否提供一个思路呢 有代码共享更好 谢谢 winkle 发表于 2013-1-16 18:15 static/image/common/back.gif
可否提供一个思路呢 有代码共享更好 谢谢
用移位寄存器
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