QuartusII警告 Removed fan-outs from the following always-disabled I/O buffe...
本帖最后由 orange-208 于 2012-12-30 11:00 编辑如题，Quartus II的警告，这个怎么解决？
Warning (13027): Removed fan-outs from the following always-disabled I/O buffers
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
Warning (13028): Removed fan-out from the always-disabled I/O buffer "dataout" to the node "dataout"
有请高手！ 代码如下：
module ram( dataout, addr, wr, rd, cs, datain );
output dataout;
input addr;
input datain;
input cs, wr, rd;
reg datastore;
reg dataout;
//write data
always @ ( wr, cs, addr, datastore, datain )
begin
if( cs == 0 )
begin
if( wr )
begin
datastore = datain;
end
else
begin
dataout = 8'bz;
end
end
end
//read data
always @ ( rd, cs, addr, datastore )
begin
if( cs == 0 )
begin
if( rd )
begin
dataout = datastore;
end
else
begin
dataout = 8'bz;
end
end
end
endmodule 说实在这个代码问题很多 Fourier00 发表于 2012-12-30 11:23 static/image/common/back.gif
说实在这个代码问题很多
能指点下吗？谢了！ 1.ram的读写操作必须用到时序逻辑；
2.状态机有3种实现，你写的这种不在这三者之一；
3.你没有控制读写之间的冲突问题，有潜在的读的同时又在写；
4.最后一点，最为重要：自己的写的ram如果写的好的话软件会帮你用片上m4k综合，没写好的话就会用le综合。前者的话什么事都没有，后者的话如果你定义深度大的话就会出现灾难。所以建议ip实现。 wuyuehang 发表于 2012-12-30 16:30 static/image/common/back.gif
1.ram的读写操作必须用到时序逻辑；
2.状态机有3种实现，你写的这种不在这三者之一；
3.你没有控制读写之间 ...
受教了！{:smile:} 这个代码貌似靠谱！
/*******************************************************************
** Creation date : 2012-12-30
** Function Description : ram
** Hardware platform : DE2-115
*******************************************************************/
`timescale 1 ns/ 1 ns
`define delay 10 //Clock-to-output delay,
//Zero time delays can be confusing
//and sometimes cause problems
`define ram_width 8 //Width of ram (number of bits)
`define ram_depth 16 //Depth of ram (number of bytes)
`define addr_size 4 //Number of bits required to
//represent the RAM address
module ram( clk, wr, rd, addr, datain, dataout );
output[`ram_width-1:0] dataout; //Data output
input[`ram_width-1:0] datain; //Data input
input[`addr_size-1:0] addr; //Menory address
input clk;
input wr, rd; //Low active
wire[`ram_width-1:0] datain, dataout;
wire[`addr_size-1:0] addr;
wire wr, rd;
reg[`ram_width-1:0] mem[`ram_depth-1:0]; //Define RAM
assign #`delay dataout = rd ? `ram_width'bz : mem;
always @ ( posedge clk )
begin
if( !wr )
begin
mem = datain;
end
end
endmodule
页:
[1]