电梯控制模块求指导。谢了、、
不知道为什么，door总是没有输出，show总是00000110.希望大牛可以指导一下。感激不尽。。。
module control(clk,up,down,floor,reset,show,door,cur_floor,stop);
input clk;//20MHz
input up;//1,2楼门外的上升请求；
input down;//3,2楼门外的下降请求；
input floor;//电梯内的楼层请求；
input reset;
output show;//楼层显示；
output door,stop;//门控制输出，1开，0关；电梯状态输出，1停，0运行；
output cur_floor;//当前楼层
reg consignal,ce_count;//用于控制开关门以及上升下降的延时；
reg cur_floor;
reg door,stop;
reg cur_state,next_state;
reg show;
reg updown;//标记电梯的前一个状态，3上升，2等待，1下降；
reg count;//计数；
parameter floor1=8'h00,
floor2=8'h01,
floor3=8'h02,
deng1=8'h03,
lift1=8'h04,
lift2=8'h05,
down3=8'h06,
down2=8'h07,
open1=8'h08,
close1=8'h09,
open2=8'h0a,
close2=8'h0b,
open3=8'h0c,
close3=8'h0d,
delay1_2=8'h0e,
delay2_3=8'h0f,
delay3_2=8'h10,
delay2_1=8'h11,
delay1=8'h12,
delay2=8'h13,
delay3=8'h14;
always @(posedge clk)
begin
cur_state<=next_state;
end
always @(posedge clk or posedge reset)
begin
if(reset==1)
next_state<=floor1;
else
case(cur_state)
floor1:
begin
if(up || floor)
next_state<=open1;
else
if(up!=0 || down!=0)
next_state<=lift1;
else
next_state<=deng1;
end
lift1:
begin
updown<=3;
next_state<=delay1_2;
end
delay1_2:
begin
if(consignal)
next_state<=floor2;
else
next_state<=delay1_2;
end
floor2:
begin
if(updown==3)
begin
if(up || floor)
begin
next_state<=open2;
if(down || floor)
updown<=3;
else
updown<=2;
end
else
next_state<=lift2;
end
else
if(updown==1)
begin
if(down || floor)
next_state<=open2;
else
next_state<=down2;
end
end
lift2:
begin
updown<=3;
next_state<=delay2_3;
end
delay2_3:
begin
if(consignal)
next_state<=floor3;
else
next_state<=delay2_3;
end
floor3:
begin
if(down || floor)
next_state<=open3;
else
next_state<=down3;
end
down3:
begin
updown<=1;
next_state<=delay3_2;
end
open1:
begin
next_state<=delay1;
end
delay1:
begin
if(consignal)
next_state<=close1;
else
next_state<=delay1;
end
close1:
begin
next_state<=floor1;
end
open2:
begin
next_state<=delay2;
end
delay2:
begin
if(consignal)
next_state<=close2;
else
next_state<=delay2;
end
close2:
begin
next_state<=floor2;
end
open3:
begin
next_state<=delay3;
end
delay3:
begin
if(consignal)
next_state<=close3;
else
next_state<=delay3;
end
close3:
begin
next_state<=floor3;
end
delay3_2:
begin
if(consignal)
next_state<=floor2;
else
next_state<=delay3_2;
end
down2:
begin
updown<=1;
next_state<=delay2_1;
end
delay2_1:
begin
if(consignal)
next_state<=floor1;
else
next_state<=delay2_1;
end
deng1:
begin
if(up!=0 || down!=0 || floor!=0)
next_state<=floor1;
else
next_state<=deng1;
end
endcase
end
always @(cur_state)
begin
case(cur_state)
floor1:
begin
show<=8'b00000110;
cur_floor<=1;
end
floor2:
begin
show<=8'b01011011;
cur_floor<=2;
end
floor3:
begin
show<=8'b01001111;
cur_floor<=3;
end
lift1:
begin
show<=8'b00000110;
end
lift2:
begin
show<=8'b01011011;
end
down3:
begin
show<=8'b01001111;
end
down2:
begin
show<=8'b01011011;
end
deng1:
begin
show<=8'b00000110;
end
open1:
begin
stop<=1;
door<=1;
ce_count<=1;
show<=8'b00000110;
end
close1:
begin
stop<=0;
door<=0;
ce_count<=0;
end
open2:
begin
stop<=1;
door<=1;
ce_count<=1;
show<=8'b01011011;
end
close2:
begin
stop<=0;
door<=0;
ce_count<=0;
end
open3:
begin
stop<=1;
door<=1;
ce_count<=1;
show<=8'b01001111;
end
close3:
begin
stop<=0;
door<=0;
ce_count<=0;
end
delay1:
begin
show<=8'b00000110;
end
delay2:
begin
show<=8'b01011011;
end
delay3:
begin
show<=8'b01001111;
end
delay1_2:
begin
show<=8'b00000110;
end
delay2_3:
begin
show<=8'b01011011;
end
delay3_2:
begin
show<=8'b01001111;
end
delay2_1:
begin
show<=8'b01011011;
end
endcase
end
always @(negedge clk)
begin
if(!ce_count)
begin
consignal<=0;
count<=20000000;
end
else
begin
if(count>1)
begin
consignal<=0;
count<=count-1;
end
else
consignal<=1;
end
end
endmodule
{:sweat:}{:sweat:} 想办法学会调试.一步一步跟踪信号. zhangalex88 发表于 2012-12-6 23:22 static/image/common/back.gif
想办法学会调试.一步一步跟踪信号.
表示不是很懂 本帖最后由 sky5566 于 2012-12-7 02:35 编辑
猜 always @(cur_state)改 always @(clk)
always @(posedge clk)
begin
cur_state<=next_state; // -->>>next_state<=deng1; 為什麼不直接寫 cur_state <=deng1 一個上緣就完成?
end
一個上緣"設",一個下緣收
所以 always @(cur_state)改 always @(negedge clk) 用Modelsim或SignalTap II仿真看看，程序没有详细看。
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