俺的第一个可以实现功能的Verilog代码，
实现stm32经过FPGA访问SRAM，让大家见笑了module bus(
addr_arm,data_arm,ctr_arm,addr_l,
data_l,ctr_l,);
input addr_arm;
inout data_arm;
input ctr_arm;
inout data_l;
outputaddr_l;
output ctr_l;
assignaddr_l=addr_arm;
assignctr_l=ctr_arm;
assigndata_arm=ctr_arm?data_l:16'bz;
assigndata_l=ctr_arm?16'bz:data_arm;
endmodule
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