谁能提供一个Verilog编写的LED扫描程序??
本帖最后由 jjj 于 2012-11-13 16:17 编辑谁能提供一个Verilog编写的LED点阵显示屏扫描程序??CPLD,FPGA都可以,外扩两片SRAM,还有一个总线与arm相连,我只想知道FPGA里的的代码,给个能用的参考就行,刚学FPGA,不知道怎么下手,
拒绝伸手党,现在将我修改过的代码贴出来,供像我这样的新手一起学习进步, 从基础学起,不要做伸手党~ 万事开头难,慢慢啃吧 这样吧,我先把我掌握的代码贡献出来!!
//
//module gray_grade(rst,pclk,vsync,link_i,link_o,row,lock,ser_clk,
module large_led(rst,pclk,link_i,link_o,row,lock,ser_clk,
en,oe,le,str,addr_arm,data_arm,ctr_arm,addr_l,
data_l,ctr_l,addr_r,data_r,ctr_r,data,led);
input rst,pclk,link_i;
input addr_arm;
input data_arm;
input ctr_arm;
inout data_l,data_r;
output addr_l,addr_r;
output ctr_l,ctr_r; //willow changeCE OE WR (UB LB)
output link_o;
output row;
output lock,ser_clk,en,le,oe,str;
output data;
output led;
wire count_addr;
wire addr_bit;
wire addr_colum;
wire addr_row;
wire frame,clk;
wire l_r;
signal signal1(rst,clk,pclk,frame,row,link_i,link_o,
ser_clk,lock,str,addr_bit,l_r,addr_colum,
addr_row,count_addr);
wr_rd wr_rd1(addr_arm,data_arm,ctr_arm,addr_l,data_l,
ctr_l,addr_r,data_r,ctr_r,data,l_r,addr_colum,addr_row,count_addr,
oe,le);
machine machine1(clk,str,en,rst,led);
endmodule
////contrl signal module
module signal(rst,clk,pclk,frame,row,link_i,link_o,
ser_clk,lock,str,addr_bit,l_r,addr_colum,
addr_row,count_addr);
output frame,link_o,lock,ser_clk,str,l_r;
output addr_colum;
output addr_bit;
output row,addr_row;
output clk;
output count_addr;
input pclk,link_i,rst;
parameter colum_num =13'd31,
row_num =10'd15; //row_num maybe 4 or 8 or 16;
//reg colum_num; //willow add ,using beforeinitial; MAX=8192
//reg row_num; // MAX=1024
reg count1; //colum count
reg count_addr; //willow add
reg row;
reg sel;
reg frame,link_o,ser_clk,lock,str,l_r,en,clk;
reg clk_div;
assign addr_colum =~count1;
assign addr_row =row;
//assign clk =clk_div;
always @(posedge pclk) //divide input clk
begin
clk_div<=clk_div+1'b1;
clk <=clk_div;
//clk=~clk;
end
always @(posedge clk) //creat the row signal,counted the clk signal when 1024 is reach,row add one
if(!rst)
begin
row <=4'b0000;
count1 <=13'b0_0000_0000_0000;
count_addr<=16'h0000;
end
else
if(count1==colum_num)
if(row==row_num)
begin
row <=4'b0000;
count1 <=13'b0;
count_addr<=16'h0000;
end
else
begin
row <=row+1;
count1 <=13'b0;
end
else
begin
row <=row;
count1 <=count1+1;
count_addr <=count_addr+1;
end
always @(posedge clk) //creat frame signal
if(row==row_num) //row_num maybe 4 or 8 or 16;
if(count1==colum_num) // 32< colum_num<8192;
frame<=1'b0;
else
frame<=1'b1;
else
frame<=1'b1;
always @(posedge clk) //assign the link_o signal base on the link_i signal
if(!frame)
if(link_i&&(!link_o))
begin
l_r <=~l_r;
link_o <=1'b1;
end
else
link_o <=link_i;
else
if(!link_i)
link_o <=1'b0;
always @(negedge clk) //lock is used to lock the odd addmss data
if((!frame)||(!rst))
//lock <=1'b0;
lock <=1'b1;
else
lock <=~lock;
always @(negedge clk) //ser_clk is used to transmit the data to the led screen
if(lock)
ser_clk<=1'b1;
else
ser_clk<=1'b0;
always @(posedge clk)
if(!frame)
str<=1'b0;
else
if(count1==colum_num)
str<=1'b1;
else
str<=1'b0;
endmodule
//��Ӱʱ�䷢��ģ��
module machine(clk,str,en,rst_n,led);
input clk;
input str;
input rst_n;
output led;
output en;
reg en;
reg count1;
parameter light0=9'b0_0000_1111;
always@(posedge clk) //generate en signal��en is low voltage effect
if(str)
begin
en<=0;
count1<=0;
end
else
begin
if(count1==light0)
en<=1;
else
begin
count1<=count1+1;
en<=0;
end
end
reg cnt; //
//reg cnt;
always @ (posedge clk or negedge rst_n)
if(!rst_n) cnt <= 23'd0;
else cnt <= cnt+1'b1; //cnt 20ms
//----------------------------------------------------
reg clk_div_r; //clk_div
always @ (posedge clk or negedge rst_n)
if(!rst_n) clk_div_r <= 1'b0;
else if(cnt == 23'hffffff)
begin
//cnt<=0;
clk_div_r <= ~clk_div_r; //ÿ20ms��clk_div_rֵ��תһ��
end
assign led = clk_div_r;
endmodule //ģ���ģ��洢���л�����ģ��
module wr_rd(addr_arm,data_arm,ctr_arm,addr_l,data_l,ctr_l,
addr_r,data_r,ctr_r,data,l_r,addr_colum,addr_row,count_addr,
oe,le);
input addr_arm;
input data_arm;
input addr_colum;
input addr_row;
input count_addr;
input ctr_arm;
input l_r;
output addr_l,addr_r;
output ctr_l,ctr_r;
output oe,le;
inout data_l,data_r;
output data;
assign data_r =l_r?data_arm:16'bzzzzzzzzzzzzzzzz; //when l_r write ram r,read ram_l
assign addr_r =l_r?addr_arm:count_addr;
assign ctr_r =l_r?ctr_arm:5'b001; //wroecs
assign data_l =l_r?16'bzzzzzzzzzzzzzzzz:data_arm; //when !l_r read ram r,write ram_l
//assign addr_l =l_r?{1'b0,addr_bit,addr_row,addr_colum}:addr_arm;
assign addr_l =l_r?count_addr:addr_arm;
assign ctr_l =l_r?5'b001:ctr_arm;
assign data =l_r?data_l:data_r;
//assign oe =vsync?1'b0:1'b1; //rst��373��374 effect
//assign le =vsync?1'b1:1'b0; //rst��373��374 effect
endmodule 大家一起来讨论,
高手来指点,
像我这样的新手一学习。
共同进步
/*-----版权声明-----
* 艾米电子工作室——让开发变得更简单
* 网站:http://www.amy-studio.com
* 淘宝:http://amy-studio.taobao.com
* QQ(邮箱):amy-studio@qq.com
*-----文件信息-----
* 文件名称:matrixKeyboard_seg7.v
* 最后修改日期:2.11, 2010
* 描述:读取矩阵键盘的值,并显示在SEG7
* SEG为0,与之对比
*------------------
* 创建者:张亚峰
* 创建日期:2.11, 2010
* 版本:1.0
* 描述:原始版本
*------------------
* 修改者:
* 修改日期:
* 版本:
* 描述:
*-------------------
*/
module matrixKeyboard_seg7(
input CLOCK_50, // 板载50MHz时钟
input Q_KEY, // 板载按键RST
input ROW, // 矩阵键盘 行
output COL, // 矩阵键盘 列
output SEG7_SEG, // 七段数码管 段脚
output SEG7_SEL // 七段数码管 待译位脚
);
//++++++++++++++++++++++++++++++++++++++
// 获取键盘值 开始
//++++++++++++++++++++++++++++++++++++++
wire keyboard_val;
matrixKeyboard_drive u0(
.i_clk (CLOCK_50),
.i_rst_n (Q_KEY),
.row (ROW),
.col (COL),
.keyboard_val (keyboard_val) // 键盘值
);
//-------------------------------------
// 获取键盘值 结束
//-------------------------------------
//+++++++++++++++++++++++++++++++++++++
// 显示键盘值 开始
//+++++++++++++++++++++++++++++++++++++
seg7x8_drive u1(
.i_clk (CLOCK_50),
.i_rst_n (Q_KEY),
.i_turn_off (8'b1111_1100), // 熄灭位[此处设置为第2~7位
.i_dp (8'b0000_0000), // 小数点位[此处未设置
.i_data ({28'h0, keyboard_val}), // 欲显数据[数据显示在SEG7
.o_seg (SEG7_SEG),
.o_sel (SEG7_SEL)
);
//-------------------------------------
// 显示键盘值 结束
//-------------------------------------
endmodule
-----------------------------------------------------------------------------
/*-----版权声明-----
* 艾米电子工作室——让开发变得更简单
* 网站:http://www.amy-studio.com
* 淘宝:http://amy-studio.taobao.com
* QQ(邮箱):amy-studio@qq.com
*-----文件信息-----
* 文件名称:matrixKeyboard_drive.v
* 最后修改日期:2.11, 2010
* 描述:矩阵键盘驱动
*------------------
* 创建者:张亚峰
* 创建日期:2.11, 2010
* 版本:1.0
* 描述:原始版本
*------------------
* 修改者:
* 修改日期:
* 版本:
* 描述:
*-------------------
*/
module matrixKeyboard_drive(
input i_clk,
input i_rst_n,
input row, // 矩阵键盘 行
output reg col, // 矩阵键盘 列
output reg keyboard_val // 键盘值
);
//++++++++++++++++++++++++++++++++++++++
// 分频部分 开始
//++++++++++++++++++++++++++++++++++++++
reg cnt; // 计数子
always @ (posedge i_clk, negedge i_rst_n)
if (!i_rst_n)
cnt <= 0;
else
cnt <= cnt + 1'b1;
wire key_clk = cnt; // (2^20/50M = 21)ms
//--------------------------------------
// 分频部分 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 状态机部分 开始
//++++++++++++++++++++++++++++++++++++++
// 状态数较少,独热码编码
parameter NO_KEY_PRESSED = 6'b000_001;// 没有按键按下
parameter SCAN_COL0 = 6'b000_010;// 扫描第0列
parameter SCAN_COL1 = 6'b000_100;// 扫描第1列
parameter SCAN_COL2 = 6'b001_000;// 扫描第2列
parameter SCAN_COL3 = 6'b010_000;// 扫描第3列
parameter KEY_PRESSED = 6'b100_000;// 有按键按下
reg current_state, next_state; // 现态、次态
always @ (posedge key_clk, negedge i_rst_n)
if (!i_rst_n)
current_state <= NO_KEY_PRESSED;
else
current_state <= next_state;
// 根据条件转移状态
always @ *
case (current_state)
NO_KEY_PRESSED : // 没有按键按下
if (row != 4'hF)
next_state = SCAN_COL0;
else
next_state = NO_KEY_PRESSED;
SCAN_COL0 : // 扫描第0列
if (row != 4'hF)
next_state = KEY_PRESSED;
else
next_state = SCAN_COL1;
SCAN_COL1 : // 扫描第1列
if (row != 4'hF)
next_state = KEY_PRESSED;
else
next_state = SCAN_COL2;
SCAN_COL2 : // 扫描第2列
if (row != 4'hF)
next_state = KEY_PRESSED;
else
next_state = SCAN_COL3;
SCAN_COL3 : // 扫描第3列
if (row != 4'hF)
next_state = KEY_PRESSED;
else
next_state = NO_KEY_PRESSED;
KEY_PRESSED : // 有按键按下
if (row != 4'hF)
next_state = KEY_PRESSED;
else
next_state = NO_KEY_PRESSED;
endcase
reg key_pressed_flag; // 键盘按下标志
reg col_val, row_val; // 列值、行值
// 根据次态,给相应寄存器赋值
always @ (posedge key_clk, negedge i_rst_n)
if (!i_rst_n)
begin
col <= 4'h0;
key_pressed_flag <= 0;
end
else
case (next_state)
NO_KEY_PRESSED : // 没有按键按下
begin
col <= 4'h0;
key_pressed_flag <= 0; // 清键盘按下标志
end
SCAN_COL0 : // 扫描第0列
col <= 4'b1110;
SCAN_COL1 : // 扫描第1列
col <= 4'b1101;
SCAN_COL2 : // 扫描第2列
col <= 4'b1011;
SCAN_COL3 : // 扫描第3列
col <= 4'b0111;
KEY_PRESSED : // 有按键按下
begin
col_val <= col; // 锁存列值
row_val <= row; // 锁存行值
key_pressed_flag <= 1; // 置键盘按下标志
end
endcase
//--------------------------------------
// 状态机部分 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 扫描行列值部分 开始
//++++++++++++++++++++++++++++++++++++++
always @ (posedge key_clk, negedge i_rst_n)
if (!i_rst_n)
keyboard_val <= 4'h0;
else
if (key_pressed_flag)
case ({col_val, row_val})
8'b1110_1110 : keyboard_val <= 4'h0;
8'b1110_1101 : keyboard_val <= 4'h4;
8'b1110_1011 : keyboard_val <= 4'h8;
8'b1110_0111 : keyboard_val <= 4'hC;
8'b1101_1110 : keyboard_val <= 4'h1;
8'b1101_1101 : keyboard_val <= 4'h5;
8'b1101_1011 : keyboard_val <= 4'h9;
8'b1101_0111 : keyboard_val <= 4'hD;
8'b1011_1110 : keyboard_val <= 4'h2;
8'b1011_1101 : keyboard_val <= 4'h6;
8'b1011_1011 : keyboard_val <= 4'hA;
8'b1011_0111 : keyboard_val <= 4'hE;
8'b0111_1110 : keyboard_val <= 4'h3;
8'b0111_1101 : keyboard_val <= 4'h7;
8'b0111_1011 : keyboard_val <= 4'hB;
8'b0111_0111 : keyboard_val <= 4'hF;
endcase
//--------------------------------------
//扫描行列值部分 结束
//--------------------------------------
endmodule
------------------------------------------------------------------------------
/*-----版权声明-----
* 艾米电子工作室——让开发变得更简单
* 网站:http://www.amy-studio.com
* 淘宝:http://amy-studio.taobao.com
* QQ(邮箱):amy-studio@qq.com
*-----文件信息-----
* 文件名称:seg7x8_drive.v
* 最后修改日期:1.29, 2010
* 描述:seg7x8动态显示驱动
*------------------
* 创建者:张亚峰
* 创建日期:1.29, 2010
* 版本:1.0
* 描述:原始版本
*------------------
* 修改者:
* 修改日期:
* 版本:
* 描述:
*-------------------
*/
module seg7x8_drive(
input i_clk,
input i_rst_n,
inputi_turn_off, // 熄灭位[2进制
inputi_dp, // 小数点位[2进制
input i_data, // 欲显数据[16进制
output o_seg, // 段脚
output o_sel // 使用74HC138译出位脚
);
//++++++++++++++++++++++++++++++++++++++
// 分频部分 开始
//++++++++++++++++++++++++++++++++++++++
reg cnt; // 计数子
always @ (posedge i_clk, negedge i_rst_n)
if (!i_rst_n)
cnt <= 0;
else
cnt <= cnt + 1'b1;
wire seg7_clk = cnt; // (2^17/50M = 2.6114)ms
//--------------------------------------
// 分频部分 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 动态扫描, 生成seg7_addr 开始
//++++++++++++++++++++++++++++++++++++++
reg seg7_addr; // 第几个seg7
always @ (posedge seg7_clk, negedge i_rst_n)
if (!i_rst_n)
seg7_addr <= 0;
else
seg7_addr <= seg7_addr + 1'b1;
//--------------------------------------
// 动态扫描, 生成seg7_addr 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 译出位码 开始
//++++++++++++++++++++++++++++++++++++++
reg o_sel_r; // 位选码寄存器
// 开发板上SEG7的方向是低位在左,高位在右
// 但是实际上我们看数的方向是高位在左,低位在右
// 故此处将第0位对应DIG,第7位对应DIG
always
case (seg7_addr)
0 : o_sel_r = 3'b111; // SEG7
1 : o_sel_r = 3'b110; // SEG7
2 : o_sel_r = 3'b101; // SEG7
3 : o_sel_r = 3'b100; // SEG7
4 : o_sel_r = 3'b011; // SEG7
5 : o_sel_r = 3'b010; // SEG7
6 : o_sel_r = 3'b001; // SEG7
7 : o_sel_r = 3'b000; // SEG7
endcase
//--------------------------------------
// 根据seg7_addr, 译出位码 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 选择熄灭码 开始
//++++++++++++++++++++++++++++++++++++++
reg turn_off_r; // 熄灭码
always
case (seg7_addr)
0 : turn_off_r = i_turn_off;
1 : turn_off_r = i_turn_off;
2 : turn_off_r = i_turn_off;
3 : turn_off_r = i_turn_off;
4 : turn_off_r = i_turn_off;
5 : turn_off_r = i_turn_off;
6 : turn_off_r = i_turn_off;
7 : turn_off_r = i_turn_off;
endcase
//--------------------------------------
// 根据seg7_addr, 选择熄灭码 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 选择小数点码 开始
//++++++++++++++++++++++++++++++++++++++
reg dp_r; // 小数点码
always
case (seg7_addr)
0 : dp_r = i_dp;
1 : dp_r = i_dp;
2 : dp_r = i_dp;
3 : dp_r = i_dp;
4 : dp_r = i_dp;
5 : dp_r = i_dp;
6 : dp_r = i_dp;
7 : dp_r = i_dp;
endcase
//--------------------------------------
// 根据seg7_addr, 选择小数点码 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 选择待译段码 开始
//++++++++++++++++++++++++++++++++++++++
reg seg_data_r; // 待译段码
always
case (seg7_addr)
0 : seg_data_r = i_data;
1 : seg_data_r = i_data;
2 : seg_data_r = i_data;
3 : seg_data_r = i_data;
4 : seg_data_r = i_data;
5 : seg_data_r = i_data;
6 : seg_data_r = i_data;
7 : seg_data_r = i_data;
endcase
//--------------------------------------
// 根据seg7_addr, 选择待译段码 结束
//--------------------------------------
//++++++++++++++++++++++++++++++++++++++
// 根据熄灭码/小数点码/待译段码
// 译出段码,开始
//++++++++++++++++++++++++++++++++++++++
reg o_seg_r; // 段码寄存器
/*
* 0
*-------
*| |
* 5|6|1
*-------
*| |
* 4| |2
*------- . 7
* 3
*/
// 共阳
always @ (posedge i_clk, negedge i_rst_n)
if (!i_rst_n)
o_seg_r <= 8'hFF; // 送熄灭码
else
if(turn_off_r) // 送熄灭码
o_seg_r <= 8'hFF;
else
if(!dp_r)
case(seg_data_r) // 无小数点
4'h0 : o_seg_r <= 8'hC0;
4'h1 : o_seg_r <= 8'hF9;
4'h2 : o_seg_r <= 8'hA4;
4'h3 : o_seg_r <= 8'hB0;
4'h4 : o_seg_r <= 8'h99;
4'h5 : o_seg_r <= 8'h92;
4'h6 : o_seg_r <= 8'h82;
4'h7 : o_seg_r <= 8'hF8;
4'h8 : o_seg_r <= 8'h80;
4'h9 : o_seg_r <= 8'h90;
4'hA : o_seg_r <= 8'h88;
4'hB : o_seg_r <= 8'h83;
4'hC : o_seg_r <= 8'hC6;
4'hD : o_seg_r <= 8'hA1;
4'hE : o_seg_r <= 8'h86;
4'hF : o_seg_r <= 8'h8E;
endcase
else
case(seg_data_r) // 加小数点
4'h0 : o_seg_r <= 8'hC0 ^ 8'h80;
4'h1 : o_seg_r <= 8'hF9 ^ 8'h80;
4'h2 : o_seg_r <= 8'hA4 ^ 8'h80;
4'h3 : o_seg_r <= 8'hB0 ^ 8'h80;
4'h4 : o_seg_r <= 8'h99 ^ 8'h80;
4'h5 : o_seg_r <= 8'h92 ^ 8'h80;
4'h6 : o_seg_r <= 8'h82 ^ 8'h80;
4'h7 : o_seg_r <= 8'hF8 ^ 8'h80;
4'h8 : o_seg_r <= 8'h80 ^ 8'h80;
4'h9 : o_seg_r <= 8'h90 ^ 8'h80;
4'hA : o_seg_r <= 8'h88 ^ 8'h80;
4'hB : o_seg_r <= 8'h83 ^ 8'h80;
4'hC : o_seg_r <= 8'hC6 ^ 8'h80;
4'hD : o_seg_r <= 8'hA1 ^ 8'h80;
4'hE : o_seg_r <= 8'h86 ^ 8'h80;
4'hF : o_seg_r <= 8'h8E ^ 8'h80;
endcase
//--------------------------------------
// 根据熄灭码/小数点码/待译段码
// 译出段码,结束
//--------------------------------------
assign o_sel = o_sel_r; // 寄存器输出位选码
assign o_seg = o_seg_r; // 寄存器输出段码
endmodule
ifeng_com 发表于 2012-11-13 16:07 static/image/common/back.gif
/*-----版权声明-----
* 艾米电子工作室——让开发变得更简单
* 网站:http://www.amy-stu ...
多谢支持,但我要的是控制LED点阵显示屏的程序,不是数码管 //21EDA的学习板
module led_8x8_a (clk,rst,dataout,en);
input clk,rst; //系统时钟50M输入 从12脚输入。
output dataout; //数码管的段码输出
output en; //数码管的位选使能输出
reg dataout;
reg en;
reg cnt_scan;//扫描频率计数器
reg dataout_buf;
always@(posedge clk or negedgerst)
begin
if(!rst) begin
cnt_scan<=0;
end
else begin
cnt_scan<=cnt_scan+1;
end
end
always @(cnt_scan)
begin
case(cnt_scan)
3'b000 :
en = 8'b1111_1110;
3'b001 :
en = 8'b1111_1101;
3'b010 :
en = 8'b1111_1011;
3'b011 :
en = 8'b1111_0111;
3'b100 :
en = 8'b1110_1111;
3'b101 :
en = 8'b1101_1111;
3'b110 :
en = 8'b1011_1111;
3'b111 :
en = 8'b0111_1111;
default :
en = 8'b1111_1110;
endcase
end
always@(en) //对应COM信号给出各段数据
begin
case(en)
8'b1111_1110:
dataout_buf=0;
8'b1111_1101:
dataout_buf=1;
8'b1111_1011:
dataout_buf=2;
8'b1111_0111:
dataout_buf=3;
8'b1110_1111:
dataout_buf=4;
8'b1101_1111:
dataout_buf=5;
8'b1011_1111:
dataout_buf=6;
8'b0111_1111:
dataout_buf=7;
default:
dataout_buf=8;
endcase
end
always@(dataout_buf)
begin
//在点阵上面显示一个爱心需要的点阵代码
case(dataout_buf)
4'b0000:
dataout=8'b11111111;
4'b0001:
dataout=8'b11111111;
4'b0010:
dataout=8'b10011001;
4'b0011:
dataout=8'b01100110;
4'b0100:
dataout=8'b01111110;
4'b0101:
dataout=8'b10111101;
4'b0110:
dataout=8'b11011011;
4'b0111:
dataout=8'b11100111;
endcase
end
endmodule wangshaosh123 发表于 2012-11-13 16:45 static/image/common/back.gif
//21EDA的学习板
再重复一遍,不要数码管,要点阵屏 本帖最后由 wangshaosh123 于 2012-11-13 18:45 编辑
jjj 发表于 2012-11-13 17:36 static/image/common/back.gif
再重复一遍,不要数码管,要点阵屏
注释是错的
这个就是点阵 数码管能显示心形吗????
而且数码管扫描和点阵扫描本来就差不多的东西就是形状不一样 编码不一样而已
学习要知道变通~~~ module dot(clk,rst_n,a,b,c,d,en,di,sclk,lclk);
input clk;
input rst_n;
output a,b,c,d,en,di,sclk,lclk;
regsclk,di;
reg cnt1;
reg cnt2;
reg wei;
reg data;
reg s;
reg lclk;
assign a=wei;
assign b=wei;
assign c=wei;
assign d=wei;
assign en = 0;
parameter sclk_div_vaule = 1000;
parameter lclk_div_vaule = 16;
always@(posedge lclk or negedge rst_n)
begin
if(!rst_n)
wei <= 'h0;
else
wei <= wei+1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt1 <= 'h0;
sclk <= 'b0;
end
else
if(cnt1 >= sclk_div_vaule)
begin
cnt1 <=0;
sclk <=~ sclk;
end
else
begin
sclk <= sclk;
cnt1 <= cnt1 + 1;
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
lclk <= 'b0;
end
else
if(cnt_di== 0)
begin
lclk <= 1;
end
else
begin
lclk <= 0;
end
end
reg cnt_di;
always@(posedge sclk or negedge rst_n)
begin
if(!rst_n)
cnt_di <= 0;
else
cnt_di <= cnt_di + 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data <= 16'h0;
else
case(wei)
0 : data <= 16'h0200;
1 : data <= 16'h3e02;
2 : data <= 16'h01dc;
3 : data <= 16'h4008;
4 : data <= 16'h4510;
5 : data <= 16'h4490;
6 : data <= 16'h2254;
7 : data <= 16'h2374;
8 : data <= 16'h15b4;
9 : data <= 16'h091f;
10 : data <= 16'h1534;
11 : data <= 16'h1334;
12 : data <= 16'h2154;
13 : data <= 16'h6090;
14 : data <= 16'h2010;
15 : data <= 16'h0000;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
di <= 0;
else
begin
case (cnt_di)
0 :di <= data;
1 :di <= data;
2 : di <= data;
3 : di <= data;
4 : di <= data;
5 : di <= data;
6 : di <= data;
7 : di <= data;
8 : di <= data;
9 : di <= data;
10 :di <= data;
11 :di <= data;
12 :di <= data;
13 :di <= data;
14 :di <= data;
15 :di <= data;
endcase
end
end
endmodule
显示“凌"字,用595和164驱动 你可以参考下
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