状态机学习
本帖最后由 zikongxiaozi 于 2012-11-11 11:17 编辑本人想实现一个用状态机控制的16bit乘法器，但是试验下来发现使用二段式状态机无法实现，而使用一段式则可以实现，且经仿真后得到所需的效果，现在贴下本人所写代码，望高手解疑答惑，谢谢！
二段式：
module test_mult16(clk,rst_n,num,pnum,dataout,temp,done,count);
input clk;
input rst_n;
input num;
input pnum;
output temp,dataout;
output done;
output count;
//---------------------------两段式状态机，控制乘法器的三个实现步骤------------------------//
reg pstate,nstate;
parameter idle = 2'b00, add = 2'b01, shift = 2'b10;
always @ (posedge clk) begin
if (!rst_n) begin
pstate <= idle;
end
else begin
pstate <= nstate;
end
end
reg count;
reg temp_r,dataout_r;
reg done_r;
always @ (pstate) begin
case (pstate)
idle : begin
count = 5'd0;
done_r = 1'b0;
dataout_r = 32'b0;
temp_r = num;
temp_r = 16'b0;
nstate = add;
end
add : begin
if (pnum)begin
dataout_r = dataout_r + temp;
nstate = shift;
end
end
shift : begin
count = count + 1'b1;
temp_r = {temp_r,1'b0};
if (count == 5'd16) begin
nstate = idle;
done_r = 1'b1;
end
else
nstate = add;
end
default : nstate = idle;
endcase
end
wire done;
wire dataout;
wire temp;
assign done = done_r; //输出标志位表示一次乘法已经结束
assign dataout = dataout_r;
assign temp = temp_r;
endmodule
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
一段式：
module test_mult16(clk,rst_n,num,pnum,dataout,temp,done,count);
input clk;
input rst_n;
input num;
input pnum;
output temp,dataout;
output done;
output count;
//-------------------------------一段式状态机-------------------------------------//
reg pstate;
reg temp_r,dataout_r;
reg count;
reg done_r;
parameter idle = 2'b00,
add= 2'b01,
shift = 2'b11;
always @ (posedge clk or negedge rst_n)begin
if(!rst_n)begin
pstate <= idle;
end
else begin
case (pstate)
idle : begin
count <= 5'b0;
dataout_r <= 32'b0;
temp_r <= num;
temp_r <= 16'b0;
done_r <= 1'b0;
pstate <= add;
end
add : begin
if (pnum)begin
dataout_r <= dataout_r + temp;
pstate <= shift;
end
end
shift : begin
count <= count + 1'b1;
temp_r <= {temp_r,1'b0};
if (count == 5'd16) begin
done_r <= 1'b1;
count <= 5'd0;
pstate <= idle;
end
else begin
pstate <= add;
end
end
default : pstate <= idle;
endcase
end
end
wire done;
wire dataout;
wire temp;
assign done = done_r; //输出标志位表示一次乘法已经结束
assign dataout = dataout_r;
assign temp = temp_r;
endmodule
由一段式实现的状态机图和仿真：
希望能够找到二段式实现不了的原因。
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