verilog两个状态机间的状态切换关系?
使用串口接收一个命令,case(command)
16'h01: state <= 16'd1; //standby mode
16'h02: state <= 16'd2;//setup mode
16'h03: state <= 16'd4;//calibration mode
16'h04: state <= 16'd8;// transmitte data mode
16'h05: state <= 16'd16;
default:;
endcase
另外一个状态机依据上述状态进行转换,并延时计数执行命令
always @(posedge clk )
case(state)
16'd1:
begin
//test_sig1_r <= 1'b1;
state0_r <=1'b0;
state1_r <=1'b1;
if(cnt<24'd600000)
begin
cnt <=cnt+ 8'd1;
if(cnt==24'd500000)
state_change <=1'b1;
else if(cnt==24'd502000)
state_change <=1'b0;
else if(cnt==24'd503000)
end
end
16'd1:
begin
if(cnt<24'd600000)
begin
cnt <=cnt+ 8'd1;
if(cnt==24'd200000)
。。。。。。。
end
计数变量 如何赋值0,让cnt在下次command命令来到时,可以顺利计数?
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