帮忙看看这个程序是什么意义
architecture behav of rxd3 issignal tmpreg8:std_logic_vector(8 downto 0);
signal sig4: std_logic;
begin
process(sig4) --此进程完成接收数据的串并转换
begin
if (sig4'event and sig4='1') then
for i in tempreg8'high downtotempreg8'low+1 loop
tempreg8(i)<=tempreg8(i-1);
end loop;
tempreg8( tempreg8'low)<=rx;
end if;
end process;
end behav;
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