CPLD 与单片机通信的问题？？？？？
我用CPLD 与STM 8 进行通信，使用的是SPI 通信，可是STM8 发送的数据不能超过16位，超过16位CPLD 接收的数据就有错误，这是为啥啊？？？？这是STM8 的程序：voidsend_data_2(u32 x ) //24位
{
u8 i=0;
x&=0xffffffff;
//GPIO_WriteLow(DA_PORT_C,SPI_CS);//使能频率
GPIO_WriteLow(DA_PORT_C,SPI_SCK); //给两个准备脉冲
GPIO_WriteHigh(DA_PORT_C,SPI_SCK);
delay_1(50);
GPIO_WriteLow(DA_PORT_C,SPI_CS);//使能频率
GPIO_WriteLow(DA_PORT_C,SPI_SCK); //给两个准备脉冲
GPIO_WriteHigh(DA_PORT_C,SPI_SCK);
delay_1(50);
//GPIO_WriteLow(DA_PORT_C,SPI_CS);//使能频率
for(i=0;i<24;i++)
{
GPIO_WriteLow(DA_PORT_C,SPI_SCK);
if(x&0x00000001<<i)
GPIO_WriteHigh(DA_PORT_C,SPI_MISO);
else
GPIO_WriteLow(DA_PORT_C,SPI_MISO);
GPIO_WriteHigh(DA_PORT_C,SPI_SCK);
//x=x<<1;
delay_1(50);
}
GPIO_WriteHigh (DA_PORT_C,SPI_MISO);
GPIO_WriteHigh (DA_PORT_C,SPI_CS); //失能频率发送
GPIO_WriteLow(DA_PORT_C,SPI_SCK);
GPIO_WriteHigh (DA_PORT_C,SPI_SCK);
delay_1(50);
GPIO_WriteLow(DA_PORT_C,SPI_SCK);
}
这是CPLD 的程序：
parameter F=0,F0=1,F1=2,F2=3,F3=4,
F4=5,F5=6,F6=7,F7=8,F8=9,
F9=10,F10=11,F11=12,F12=13,
F13=14,F14=15,F15=16,F16=17,
F17=18,F18=19,F19=20,F20=21,
F21=22,F22=23,F23=24,F24=25,
F25=26,F26=27,F27=28;
always @ (posedge sck_rise) //当频率使能端为高点平1时，按状态顺序接受数据
begin
if(~Cs)
case (sys_state_F)
F: sys_state_F<=F0;
F0: begin
sys_state_F<=F1;
Date_int<=Sdi;
end
F1: begin
sys_state_F<=F2;
Date_int<=Sdi;
end
F2: begin
sys_state_F<=F3;
Date_int<=Sdi;
end
F3: begin
sys_state_F<=F4;
Date_int<=Sdi;
end
F4: begin
sys_state_F<=F5;
Date_int<=Sdi;
end
F5: begin
sys_state_F<=F6;
Date_int<=Sdi;
end
F6: begin
sys_state_F<=F7;
Date_int<=Sdi;
end
F7: begin
sys_state_F<=F8;
Date_int<=Sdi;
end
F8: begin
sys_state_F<=F9;
Date_int<=Sdi;
end
F9: begin
sys_state_F<=F10;
Date_int<=Sdi;
end
F10: begin
sys_state_F<=F11;
Date_int<=Sdi;
end
F11: begin
sys_state_F<=F12;
Date_int<=Sdi;
end
F12: begin
sys_state_F<=F13;
Date_int<=Sdi;
end
F13: begin
sys_state_F<=F14;
Date_int<=Sdi;
end
F14: begin
sys_state_F<=F15;
Date_int<=Sdi;
end
F15: begin
sys_state_F<=F16;
Date_int<=Sdi;
end
F16: begin
sys_state_F<=F17;
Date_int<=Sdi;
end
F17: begin
sys_state_F<=F18;
Date_int<=Sdi;
end
F18: begin
sys_state_F<=F19;
Date_int<=Sdi;
end
F19: begin
sys_state_F<=F20;
Date_int<=Sdi;
end
F20: begin
sys_state_F<=F21;
Date_int<=Sdi;
end
F21: begin
sys_state_F<=F22;
Date_int<=Sdi;
end
F22: begin
sys_state_F<=F23;
Date_int<=Sdi;
end
F23: begin
sys_state_F<=F;
Date_int<=Sdi;
end
default: sys_state_F<=F;
endcase
else
begin
sys_state_F<=F ;
end
end 怎么没人帮我看看啊，急死人啦？？？{:mad:}
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