模块中data_out的数据怎么一直在加，其解释！
如题module divider
(
clk, rstn,
Cnt1_data,
Cnt2_data,
Data_Bin
);
input clk, rstn;
input Cnt1_data;
input Cnt2_data;
output Data_Bin;
/***********************************************/
parameter Freq_50KHz = 16'd50_000; //Fs = Freq_50KHz
/***********************************************/
reg Cnt1_in, Cnt2_in; //Ns = Cnt1_in, Nx = Cnt2_in
reg Data_out; //Fx = Data_out
reg init_flag;
reg div_over;
always @ ( posedge clk or negedge rstn )
if( !rstn )
begin
Cnt1_in <= 32'd0;
Cnt2_in <= 32'd0;
Data_out <= 32'd0;
div_over <= 1'd0;
init_flag <= 1'd0;
end
else if( !init_flag )
begin
init_flag <= 1'd1;
Cnt1_in <= Cnt1_data;
Cnt2_in <= Cnt2_data * Freq_50KHz;
end
else if( ( Cnt2_in >= Cnt1_in ) && ( !div_over ) && init_flag )
begin
Cnt2_in <= Cnt2_in - Cnt1_in;
Data_out <= Data_out + 1'b1;
end
else if( Cnt2_in < Cnt1_in )
begin
div_over <= 1'd1;
end
/***********************************************/
assign Data_Bin = Data_out;
/***********************************************/
endmodule
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