（等精度频率计）divider模块测试时Data_BIN没有输出，怎么...
如题，不知道是怎么回事，代码、testbench、仿真波形 都在下面，各位给点建议，谢了！module divider
(
clk, rstn,
Cnt1_data,
Cnt2_data,
Data_Bin
);
input clk, rstn;
input Cnt1_data; //Fs limited to 50MHz
input Cnt2_data; //Fx limited to 60MHz
output Data_Bin;
/*******************************************************/
parameter Freq_50MHz = 26'd50_000_000; //Fs = Freq_50MHz
/*******************************************************/
reg Cnt1_in, Cnt2_in;//Ns = Cnt1_in, Nx = Cnt2_in
reg Data_out; //Fx = Data_out
reg flag;
always @ ( posedge clk or negedge rstn )
if( !rstn )
begin
flag = 0;
Cnt1_in <= 26'd0;
Cnt2_in <= 26'd0;
Data_out <= 52'd0;
end
else if( Cnt1_in != 26'd0 && flag == 1'b1 )
begin
Data_out <= ( Cnt2_in / Cnt1_in ) * Freq_50MHz;
end
else
begin
flag = 1'b1;
Cnt1_in <= Cnt1_data;
Cnt2_in <= Cnt2_data;
end
/**************************************/
assign Data_Bin = Data_out;
/**************************************/
endmodule
// Simulation tool : ModelSim-Altera (Verilog)
`timescale 1 ns/ 1 ns
module divider_vlg_tst();
reg Cnt1_data;
reg Cnt2_data;
reg clk;
reg rstn;
wire Data_Bin;
/*****************************/
divider i1
(
.Cnt1_data(Cnt1_data),
.Cnt2_data(Cnt2_data),
.Data_Bin(Data_Bin),
.clk(clk),
.rstn(rstn)
);
/*****************************/
initial
begin
clk = 0;
rstn = 1;
#10 rstn = 0;
#10 rstn = 1;
end
always #10 clk = ~clk;
/**************************************/
always @ ( posedge clk or negedge rstn )
if( !rstn )
begin
Cnt1_data <= 26'd0;
Cnt2_data <= 26'd0;
end
else
begin
Cnt1_data <= 26'd50_000;
Cnt2_data <= 26'd50;
end
/**************************************/
endmodule
/*******************************************************/
parameter Freq_50KHz = 16'd50_000; //Fs = Freq_50KHz
/*******************************************************/
改成这样子也没用！诚请高手指点！ 顶起！ 各位大神，有知道的吗？
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