CMOS 4021 verilog语言描述有问题?
http://forum.eet-cn.com/thread!printPreview.jspa?threadID=1200056018&start=0实际都少移一位?手册写cp 与 pl是有互斥的..
module easy(f8,f7,f6,f5,f4,f3,f2,f1,O6,O7,O8,pl,cp,ds);
input f8,f7,f6,f5,f4,f3,f2,f1;
input pl,cp,ds；
output O6,O7,O8;
reg fifo;
reg buff;
reg state1;
///////////////////////
assign O6= pl? f6: ( state1?buff:(fifo) );
assign O7= pl? f7: ( state1?buff:(fifo) );
assign O8= pl? f8: ( state1?buff:(fifo) );
/////////////////////////
always@(posedge pl or posedge cp)
if(pl)
state1<=1;
else
state1<=0;
//////////////////////////
always @(negedge pl)
buff<={f8,f7,f6,f5,f4,f3,f2,f1};
/////////////////////////
always@(posedge cp)
if(state1)
fifo<={buff,ds};
else
fifo<={fifo,ds};
////////////////////////
endmodule
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