关于警告No output dependent on input pin "T_CLK"，大侠能说说嘛？
如题，Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "T_CLK"
module Freq_counter
(
B_CLK, T_CLK, rstn,
Led_8, Led_7, Led_6, Led_5,
Led_4, Led_3, Led_2, Led_1
);
input B_CLK, T_CLK, rstn;
output Led_8, Led_7, Led_6, Led_5,
Led_4, Led_3, Led_2, Led_1;
wire B_CLK, T_CLK, rstn;
wire Led_8, Led_7, Led_6, Led_5,
Led_4, Led_3, Led_2, Led_1;
/**************************************/
wire clk_1hz;
wire gate_clk;
div_clk U1
(
.B_CLK( B_CLK ),
.rstn( rstn ),
.clk_1hz( clk_1hz ),
.gate_clk( gate_clk )
);
/**************************************/
wire Q;
d_flip_flop U2
(
.D( gate_clk ),
.CP( T_CLK ),
.rstn( rstn ),
.Q( Q )
);
/**************************************/
RTL Viewer在下面、红线部分是T_CLK的连线！
module d_flip_flop
(
D, CP, rstn,
Q
);
input D, CP, rstn;
output Q;
reg Q;
/*************************************/
always @ ( posedge CP or negedge rstn )
if( !rstn )
Q <= 1'b0;
else
Q <= D;
/*************************************/
endmodule
module counter2
(
Sig_in, CEN,
Cnt2_data
);
input Sig_in, CEN;
output Cnt2_data;
/************************************/
parameter freq_50MHz = 32'd50_000_000;
/************************************/
reg count4;
always @ ( posedge Sig_in )
if( CEN == 1'b0 )
begin
count4 <= 0;
end
else
begin
count4 <= count4 + 1'b1;
end
/**************************************/
assign Cnt2_data = count4 * freq_50MHz;
/**************************************/
endmodule
求高手解释，谢了！
顶起！ 高手留步！！！ 你的输出output Led_8, Led_7, Led_6, Led_5,Led_4, Led_3, Led_2, Led_1;
跟T_CLK没关系，编译器说的没错。
页:
[1]