帮忙看看代码，testbench文件第一次写，感觉波形不对啊？
如题下面分别是.V文件 与.Vt文件
module gate_ch
(
rstn,
gate_ch1,
gate_ch2,
gate_ch3,
clk_1hz,
clk_10hz,
clk_100hz,
clk_1khz,
gate_out,
scan_freq,
error,
flag
);
input rstn;
input gate_ch1, gate_ch2, gate_ch3;
input clk_1hz, clk_10hz, clk_100hz;
input clk_1khz;
output wire scan_freq;
output reg flag;
output reg gate_out;
output reg error;
/********************************************/
reg count5; // 产生扫描信号时的分频计数值
reg gate;
always @( posedge clk_1khz or negedge rstn )
begin
if( !rstn )
begin
flag = 2'b01;
gate <= 0;
error <= 1;
count5 <= 0;
end
else
begin
if( gate_ch1 == 0 && gate_ch2 == 1 && gate_ch3 == 1 )
begin
flag = 2'b01;
gate <= clk_1hz;
error <= 1;
end
else if( gate_ch1 == 1 && gate_ch2 == 0 && gate_ch3 == 1 )
begin
flag = 2'b10;
gate <= clk_10hz;
error <= 1;
end
else if( gate_ch1 == 1 && gate_ch2 == 1 && gate_ch3 == 0 )
begin
flag = 2'b11;
gate <= clk_100hz;
error <= 1;
end
else
begin
error <= 0;
end
end
end
/********************************************/
always @ ( posedge gate or negedge rstn )
begin
if( !rstn )
begin
gate_out <= 0;
end
else
begin
gate_out <= ~gate_out;
end
end
/********************************************/
assign scan_freq = clk_1khz;
/********************************************/
endmodule
.Vt文件如下：
`timescale 1 us/ 1 ps
module gate_ch_vlg_tst();
reg clk_1hz;
reg clk_1khz;
reg clk_10hz;
reg clk_100hz;
reg gate_ch1;
reg gate_ch2;
reg gate_ch3;
reg rstn;
// wires
wire error;
wire flag;
wire gate_out;
wire scan_freq;
/*************************/
gate_ch i1
(
.clk_1hz( clk_1hz ),
.clk_1khz( clk_1khz ),
.clk_10hz( clk_10hz ),
.clk_100hz( clk_100hz ),
.error( error ),
.flag( flag ),
.gate_ch1( gate_ch1 ),
.gate_ch2( gate_ch2 ),
.gate_ch3( gate_ch3 ),
.gate_out( gate_out ),
.rstn( rstn ),
.scan_freq( scan_freq )
);
/********************************************/
initial
begin
rstn = 0;
#10 rstn = 1;
clk_1hz = 0;
forever #500000 clk_1hz = ~clk_1hz;
clk_10hz = 0;
forever #50000 clk_10hz = ~clk_10hz;
clk_100hz = 0;
forever #5000 clk_100hz = ~clk_100hz;
clk_1khz = 0;
forever #500 clk_1khz = ~clk_1khz;
end
/********************************************/
reg item;
always @ ( posedge clk_1khz or negedge rstn )
if( !rstn )
begin
item <= 2'd1;
end
else
case( item )
1:
begin
gate_ch1 <= 0;
gate_ch2 <= 1;
gate_ch3 <= 1;
item <= 2'd2;
end
2:
begin
gate_ch1 <= 1;
gate_ch2 <= 0;
gate_ch3 <= 1;
item <= 2'd3;
end
3:
begin
gate_ch1 <= 1;
gate_ch2 <= 1;
gate_ch3 <= 0;
item <= 2'd1;
end
endcase
/********************************************/
endmodule
大侠们，给点建议，在此谢过！ 波形在这里~ .Vt 文件写好了，波形也出来了！
// Simulation tool : ModelSim-Altera (Verilog)
`timescale 1 ps/ 1 ps
module gate_ch_vlg_tst();
reg clk_1hz;
reg clk_1khz;
reg clk_10hz;
reg clk_100hz;
reg gate_ch1;
reg gate_ch2;
reg gate_ch3;
reg rstn;
// wires
wire error;
wire flag;
wire gate_out;
wire scan_freq;
/*************************/
gate_ch i1
(
.clk_1hz( clk_1hz ),
.clk_10hz( clk_10hz ),
.clk_100hz( clk_100hz ),
.clk_1khz( clk_1khz ),
.error( error ),
.flag( flag ),
.gate_ch1( gate_ch1 ),
.gate_ch2( gate_ch2 ),
.gate_ch3( gate_ch3 ),
.gate_out( gate_out ),
.rstn( rstn ),
.scan_freq( scan_freq )
);
/********************************************/
initial
begin
rstn = 1;
#10 rstn = 0;
#10 rstn = 1;
gate_ch1 = 1;
gate_ch2 = 0;
gate_ch3 = 1;
clk_1khz = 0;
forever
#500 clk_1khz = ~clk_1khz;
end
/********************************************/
initial
begin
clk_1hz = 0;
forever
#500000 clk_1hz = ~clk_1hz;
end
/********************************************/
initial
begin
clk_10hz = 0;
forever
#50000 clk_10hz = ~clk_10hz;
end
/********************************************/
initial
begin
clk_100hz = 0;
forever
#5000 clk_100hz = ~clk_100hz;
end
/********************************************/
endmodule
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