分享一个简单的Verilog状态机交通灯控制器，高手绕路、、、
module traffic_state(
clk_1Hz,
nrst,
one_data,
ten_data,
led_zhu,
led_zhi
);
input clk_1Hz, nrst;
output led_zhu; //led_zhu 红，led_zhu 黄，led_zhu 绿
output led_zhi; //led_zhi 红，led_zhi 黄，led_zhi 绿
output one_data; //倒计时个位
output ten_data; //倒计时十位
/***************四种工作状态***************/
parameter state_0 = 2'b00,
state_1 = 2'b01,
state_2 = 2'b10,
state_3 = 2'b11;
/******************************交通状态转换*****************************/
reg light_zhu; //light_zhu 红，light_zhu 黄，light_zhu 绿
reg light_zhi; //light_zhi 红，light_zhi 黄，light_zhi 绿
reg CS;
reg flag;
reg count_H, count_L;
always @ ( posedge clk_1Hz or negedge nrst )
if( !nrst )
begin
CS <= state_0;
flag <= 2'b00;
state_0_init;
end
else
case( CS )
state_0: if( flag == 2'b00 ) //状态state_0, 主干道通行35s
begin
if( !count_H && ( count_L == 4'b0110 ) ) //最后5s黄灯亮
begin
flag <= 2'b01;
CS <= state_1;
state_1_init; //初始化state_1
end
else if( !count_L )
begin
count_L <= 4'b1001;
count_H <= count_H-1'b1;
end
else
begin
count_L <= count_L-1'b1;
end
end
state_1: if( flag == 2'b01 ) //状态state_1,主干道黄灯倒计时5s
begin
if( !count_L )
begin
flag <= 2'b10;
CS <= state_2;
state_2_init; //初始化state_2
end
else
begin
count_L <= count_L-1'b1;
end
end
state_2: if( flag == 2'b10 ) //状态state_2,支干道通行25s
begin
if( !count_H && ( count_L == 4'b0110 ) ) //最后5s黄灯亮
begin
flag <= 2'b11;
CS <= state_3;
state_3_init; //初始化state_3
end
else if( !count_L )
begin
count_L <= 4'b1001;
count_H <= count_H-1'b1;
end
else
begin
count_L <= count_L-1'b1;
end
end
state_3: if( flag == 2'b11 )//状态state_3,支干道黄灯倒计时5s
begin
if( !count_L )
begin
flag <= 2'b00;
CS <= state_0;
state_0_init; //初始化state_0
end
else
begin
count_L <= count_L-1'b1;
end
end
default: begin
flag <=2'b00;
CS <= state_0;
end
endcase
/*************************************/
task state_0_init;
begin
count_H <= 4'b0011; //高位为3
count_L <= 4'b0101; //低位为5
light_zhu <= 3'b100; //light_zhu:0 , light_zhu:0 , light_zhu:1
light_zhi <= 3'b001; //light_zhi:0 , light_zhi:0 , light_zhi:1
end
endtask
/*************************************/
task state_1_init;
begin
count_H <= 4'b0000; //高位为0
count_L <= 4'b0101; //低位为5
light_zhu <= 3'b010;
light_zhi <= 3'b001;
end
endtask
/*************************************/
task state_2_init;
begin
count_H <= 4'b0010; //高位为2
count_L <= 4'b0101; //低位为5
light_zhu <= 3'b001;
light_zhi <= 3'b100;
end
endtask
/*************************************/
task state_3_init;
begin
count_H <= 4'b0000; //高位为0
count_L <= 4'b0101; //低位为5
light_zhu <= 3'b001;
light_zhi <= 3'b010;
end
endtask
/**************************/
assign one_data = count_L;
assign ten_data = count_H;
assign led_zhu = light_zhu;
assign led_zhi = light_zhi;
/**************************/
endmodule
整个工程如下@ 顶起 顶楼主 顶起来。 不错，顶楼主 帮你顶吧 新手学起 顶一下。。。。。。。。。。。。。。。。。 quartus ii seetings file contains one or more errors楼主共享的工程打不开这是怎么回事？？ 顶楼主！ 求人来教教我 感激不尽 跪求楼主共享顶层原理图！ 跪求楼主指导 quartus ii seetings file contains one or more errors 这问题，感激不尽
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