请帮忙分析fpga状态机不连续的原因，谢谢，代码如下
本帖最后由 langxing08 于 2012-8-29 10:43 编辑请问为什么我的状态机不连续啊？
我有两个状态机，一个正常，另外一个就不正常，如下图所示：
为什么呢？
没有人光看状态图就能debug的。。。。 brahen 发表于 2012-8-28 18:21 static/image/common/back.gif
没有人光看状态图就能debug的。。。。
而且是一个连跳转条件都没有的状态图 我也是很疑惑，我明明写了跳转条件的，可是编译出来就没有了... 贴上你的代码 好，明天早上把代码贴上！ module uart_top(
clk,rst_n,
txd_en,txd,txd_flag,txd_data,
rxd,rxd_flag,rxd_data
);
inputclk;
inputrst_n;
inputtxd_en; // uart发送使能
inputrxd;
output txd;
input txd_data;
output rxd_data;
output txd_flag; // uart发送完成标志位
output rxd_flag; // uart接收完成标志位
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
// SRAM:CY7C131
// Note:clk 25MHz
module SRAM_ctrl(
clk,rst_n,
sram_wr_data,sram_rd_data,sram_addr_in,
sram_wr_req,sram_rd_req,sram_wr_ok,sram_rd_ok,
sram_addr,sram_data,sram_ce_n,sram_oe_n,sram_rw,sram_busy_n
);
inputclk; // clk 25MHz
inputrst_n; // reset,low
//SRAM:CY7C131
input sram_addr_in;
output sram_addr;
inout sram_data;
input sram_wr_data;
output sram_rd_data;
output sram_ce_n;
output sram_oe_n;
output sram_rw;
inputsram_busy_n;
inputsram_wr_req;
inputsram_rd_req;
output sram_wr_ok;
output sram_rd_ok;
reg sram_addr_r;
reg sram_rd_data_r;
reg sram_ce_n_r;
reg sram_oe_n_r;
reg sram_rw_r;
//-----------------------------------------------------------
//reg sram_addr_cnt;
//always@(posedge sram_wr_req or negedge rst_n)
// if(!rst_n) sram_addr_cnt <= 10'd0;
// else sram_addr_cnt <= sram_addr_cnt + 1'b1;
//------------------------------------------------------------
//check sram_wr_req posedge edge
reg sram_wr_req_r0,sram_wr_req_r1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
sram_wr_req_r0 <= 1'b0;
sram_wr_req_r1 <= 1'b0;
end
else
begin
sram_wr_req_r0 <= sram_wr_req;
sram_wr_req_r1 <= sram_wr_req_r0;
end
wire sram_wr_req_pose = sram_wr_req_r0 & ~sram_wr_req_r1;
//check sram_rd_req posedge edge
reg sram_rd_req_r0,sram_rd_req_r1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
sram_rd_req_r0 <= 1'b0;
sram_rd_req_r1 <= 1'b0;
end
else
begin
sram_rd_req_r0 <= sram_rd_req;
sram_rd_req_r1 <= sram_rd_req_r0;
end
wire sram_rd_req_pose = sram_rd_req_r0 & ~sram_rd_req_r1;
//-----------------------------------------------------------------
// sram read and write
parameter IDLE = 4'd0,
RED1 = 4'd1,
RED2 = 4'd2,
RED3 = 4'd3,
RED4 = 4'd4,
WRT1 = 4'd5,
WRT2 = 4'd6,
WRT3 = 4'd7,
WRT4 = 4'd8,
WRT5 = 4'd9,
WRT6 = 4'd10;
reg cstate,nstate;
always@(posedge clk or negedge rst_n)
if(!rst_n) cstate <= IDLE;
else cstate <= nstate;
always@(cstate or sram_wr_req_pose or sram_rd_req_pose or sram_busy_n)
case(cstate)
IDLE: if(sram_wr_req_pose) nstate <= WRT1;
else if(sram_rd_req_pose) nstate <= RED1;
else nstate <= IDLE;
//WRITE
WRT1: nstate <= WRT2;
WRT2: nstate <= WRT3;
WRT3: nstate <= WRT4;
WRT4: if(!sram_busy_n) nstate <= WRT4;
else nstate <= WRT5;
WRT5: nstate <= WRT6;
WRT6: nstate <= IDLE;
//READ
RED1: nstate <= RED2;
RED2: nstate <= RED3;
RED3: if(!sram_busy_n) nstate <= RED3;
else nstate <= RED4;
RED4: nstate <= IDLE;
//defalult
default: nstate <= IDLE;
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
sram_ce_n_r <= 1'b1;
sram_oe_n_r <= 1'b1;
sram_rw_r <= 1'b1;
end
else
case(cstate)
IDLE: begin
sram_ce_n_r <= 1'b1;
sram_oe_n_r <= 1'b1;
sram_rw_r <= 1'b1;
end
//WRITE
WRT1: begin
sram_ce_n_r <= 1'b0;
sram_oe_n_r <= 1'b1;
sram_rw_r <= 1'b1;
end
WRT2: begin
sram_addr_r <= sram_addr_in;
end
WRT5: begin
sram_rw_r <= 1'b0;
end
WRT6: begin
sram_rw_r <= 1'b1;
end
//READ
RED1: begin
sram_ce_n_r <= 1'b0;
sram_oe_n_r <= 1'b0;
sram_rw_r <= 1'b1;
end
RED2: begin
sram_addr_r <= sram_addr_in;
end
RED4: begin
sram_rd_data_r <= sram_data;
end
default:;
endcase
assign sram_addr = sram_addr_r;
assign sram_ce_n = sram_ce_n_r;
assign sram_oe_n = sram_oe_n_r;
assign sram_rw = sram_rw_r;
assign sram_data = ((cstate == WRT3)||(cstate == WRT4)||(cstate == WRT5)||(cstate == WRT6)) ? sram_wr_data : 8'hzz;
assign sram_wr_ok = (cstate == WRT6) ? 1'b1 : 1'b0;
assign sram_rd_ok = (cstate == RED4) ? 1'b1 : 1'b0;
assign sram_rd_data = sram_rd_data_r;
//------------------------------------------------------------------------
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module SRAM(
clk,rst_n,
led,
txd,rxd,
sram_addr,sram_data,sram_ce_n,sram_oe_n,sram_rw,sram_busy_n
);
inputclk; // system clk 50MHz
inputrst_n; // system reset
wire clk25;
wire sys_rst_n;
//UART
inputrxd;
output txd;
regtxd_en;
wire txd_flag;
wire rxd_flag;
wire rxd_data;
reg txd_data;
//SRAM
inout sram_data;
output sram_addr;
output sram_rw;
output sram_ce_n;
output sram_oe_n;
inputsram_busy_n;
reg sram_wr_data;
wire sram_rd_data;
reg sram_addr_in;
regsram_wr_req;
regsram_rd_req;
wire sram_wr_ok;
wire sram_rd_ok;
//reg sram_addr_wr;
//reg sram_addr_rd;
//
//assign sram_addr_in = (sys_cstate == SYS_WR15) ?sram_addr_wr : sram_addr_rd;
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
system_ctrl u_system_ctrl(
.clk(clk),
.rst_n(rst_n),
.sys_rst_n(sys_rst_n)
);
PLL u_PLL(
.inclk0(clk),
.c0(clk25)
);
SRAM_ctrl u_SRAM_ctrl(
.clk(clk25),
.rst_n(sys_rst_n),
.sram_addr_in(sram_addr_in),
.sram_wr_data(sram_wr_data),
.sram_rd_data(sram_rd_data),
.sram_wr_req(sram_wr_req),
.sram_rd_req(sram_rd_req),
.sram_wr_ok(sram_wr_ok),
.sram_rd_ok(sram_rd_ok),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_ce_n(sram_ce_n),
.sram_oe_n(sram_oe_n),
.sram_rw(sram_rw),
.sram_busy_n(sram_busy_n)
);
uart_top u_uart_top(
.clk(clk25),
.rst_n(sys_rst_n),
.txd_en(txd_en),
.txd_data(txd_data),
.txd_flag(txd_flag),
.rxd_flag(rxd_flag),
.rxd_data(rxd_data),
.txd(txd),
.rxd(rxd)
);
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
reg rxd_bf;
reg txd_bf;
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
reg uart_recv_cnt;
integer i;
always@(posedge clk or negedge sys_rst_n)
if(!sys_rst_n)
begin
uart_recv_cnt <= 5'd0;
//shift memory
for(i=5; i>0; i=i-1)
rxd_bf <= 8'h0;
end
else if(uart_recv_cnt < 5'd5)
begin
if(rxd_flag)
begin
uart_recv_cnt <= uart_recv_cnt + 1'b1;
for(i=5; i>1; i=i-1)
rxd_bf <= rxd_bf;
rxd_bf <= rxd_data;
end
end
else if(uart_recv_cnt >= 5'd5)
uart_recv_cnt <= 5'd0;
//uart_receive_flag
reg uart_recv_flag;
reg uart_recv_flag_clr;
always@(posedge clk25 or negedge sys_rst_n)
if(!sys_rst_n) uart_recv_flag <= 1'b0;
else if(uart_recv_flag_clr) uart_recv_flag <= 1'b0;
else if(uart_recv_cnt == 5'd5) uart_recv_flag <= 1'b1;
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
parameter SYS_IDLE = 4'd0,
SYS_RECV_1 = 4'd1,
SYS_RECV_2 = 4'd2,
SYS_RECV_3 = 4'd3,
SYS_WR15_1 = 4'd4,
SYS_WR15_2 = 4'd5,
SYS_WR15_3 = 4'd6,
SYS_RD15_1 = 4'd7,
SYS_RD15_2 = 4'd8,
SYS_RD15_3 = 4'd9,
SYS_SEND_1 = 4'd10,
SYS_SEND_2 = 4'd11,
SYS_SEND_3 = 4'd12;
reg sys_cstate,sys_nstate;
always@(posedge clk25 or negedge sys_rst_n)
if(!sys_rst_n) sys_cstate <= SYS_IDLE;
else sys_cstate <= sys_nstate;
reg sram_wr15_cnt;
reg sram_rd15_cnt;
reg uart_send_cnt;
always@(*)
case(sys_cstate)
SYS_IDLE : sys_nstate = SYS_RECV_1;
SYS_RECV_1: if(uart_recv_flag) sys_nstate = SYS_RECV_2;
SYS_RECV_2: sys_nstate = SYS_RECV_3;
SYS_RECV_3: sys_nstate = SYS_WR15_1;
SYS_WR15_1: if(sram_wr_ok) sys_nstate = SYS_WR15_2;
SYS_WR15_2: if(sram_wr15_cnt < 5'd5) sys_nstate = SYS_WR15_1;
else sys_nstate = SYS_WR15_3;
SYS_WR15_3: sys_nstate = SYS_RD15_1;
SYS_RD15_1: if(sram_rd_ok) sys_nstate = SYS_RD15_2;
SYS_RD15_2: if(sram_rd15_cnt < 5'd5) sys_nstate = SYS_RD15_1;
else sys_nstate = SYS_RD15_3;
SYS_RD15_3: sys_nstate = SYS_SEND_1;
SYS_SEND_1: if(txd_flag) sys_nstate = SYS_SEND_2;
SYS_SEND_2: if(uart_send_cnt < 5'd5) sys_nstate = SYS_SEND_3;
else sys_nstate = SYS_SEND_1;
SYS_SEND_3: sys_nstate = SYS_IDLE;
default : sys_nstate = SYS_IDLE;
endcase
always@(posedge clk25 or negedge sys_rst_n)
if(!sys_rst_n)
begin
sram_wr15_cnt <= 5'd0;
sram_rd15_cnt <= 5'd0;
uart_send_cnt <= 5'd0;
sram_wr_req <= 1'b0;
sram_rd_req <= 1'b0;
end
else
case(sys_cstate)
SYS_IDLE : begin
sram_wr15_cnt <= 5'd0;
sram_rd15_cnt <= 5'd0;
uart_send_cnt <= 5'd0;
sram_wr_req <= 1'b0;
sram_rd_req <= 1'b0;
end
SYS_RECV_1: ;
SYS_RECV_2: uart_recv_flag_clr <= 1'b1;
SYS_RECV_3: uart_recv_flag_clr <= 1'b0;
SYS_WR15_1: begin
sram_wr_req<= 1'b1;
sram_addr_in <= {5'h0,sram_wr15_cnt};
sram_wr_data <= rxd_bf;
end
SYS_WR15_2: sram_wr15_cnt <= sram_wr15_cnt + 1'b1;
SYS_WR15_3: sram_wr_req<= 1'b0;
SYS_RD15_1: begin
sram_rd_req<= 1'b1;
sram_addr_in <= {5'h0,sram_rd15_cnt};
txd_bf <= sram_rd_data;
end
SYS_RD15_2: sram_rd15_cnt <= sram_rd15_cnt + 1'b1;
SYS_RD15_3: sram_rd_req<= 1'b0;
SYS_SEND_1: begin
txd_en <= 1'b1;
txd_data <= txd_bf;
end
SYS_SEND_2: uart_send_cnt <= uart_send_cnt + 1'b1;
SYS_SEND_3: txd_en <= 1'b0;
default : ;
endcase
//-------------------------------------------------------------------------
//LED
output led;
reg led_r;
always@(posedge clk25 or negedge sys_rst_n)
if(!sys_rst_n) led_r <= 4'hf;
else
case(sys_cstate)
SYS_IDLE : led_r <= 4'd1;
SYS_RECV_1: led_r <= 4'd2;
SYS_RECV_2: led_r <= 4'd3;
SYS_RECV_3: led_r <= 4'd4;
SYS_WR15_1: led_r <= 4'd5;
SYS_WR15_2: led_r <= 4'd6;
SYS_WR15_3: led_r <= 4'd7;
SYS_RD15_1: led_r <= 4'd8;
SYS_RD15_2: led_r <= 4'd9;
SYS_RD15_3: led_r <= 4'd10;
SYS_SEND_1: led_r <= 4'd11;
SYS_SEND_2: led_r <= 4'd12;
SYS_SEND_3: led_r <= 4'd13;
default : led_r <= 4'd14;
endcase
assign led = led_r;
endmodule 跳转条件为什么会消失了呢？ 优化掉了吧综合时 看看综合报告。 kebaojun305 发表于 2012-8-29 12:57 static/image/common/back.gif
优化掉了吧综合时 看看综合报告。
请问怎么看综合报告？
看哪里能找到状态机相关的信息呢？
说实话，我也是怀疑可能被编译器优化掉了，但是不知道该怎么查看。 langxing08 发表于 2012-8-29 15:16 static/image/common/back.gif
请问怎么看综合报告？
看哪里能找到状态机相关的信息呢？
打算给你看下可惜添加工程中 编译 一堆 错误你还是整个工程 或者原文件上传吧。 本帖最后由 langxing08 于 2012-8-30 13:21 编辑
上传整个工程，请大家帮忙看看！
attach://46844.rar langxing08 发表于 2012-8-30 13:10 static/image/common/back.gif
上传整个工程，请大家帮忙看看！
attach://46844.rar
先分析下每条警告要知道为啥会产生警告，解决完我估计就OK了。
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