virtex-5,PLL_ADV属性不合法
pll_dvi pll_dvi (.CLKIN1_IN(clk100),
.RST_IN(rst_n),
.CLKOUT0_OUT(clk_100),
.CLKOUT1_OUT(clk_50),
.CLKOUT2_OUT(clk_25),
.LOCKED_OUT(locked_out)
);
本人用virtex-5，在ISE12.4中，例化输入100M时钟，输出分别为100M,50M,25M，但是综合的时候却提示警告，请问该做如何处理？谢谢！
WARNING:Xst:616 - Invalid property "CLKIN_FREQ_MAX 710.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "CLKIN_FREQ_MIN 19.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "CLKPFD_FREQ_MAX 550.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "CLKPFD_FREQ_MIN 19.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "VCOCLK_FREQ_MAX 1440.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "VCOCLK_FREQ_MIN 400.000000": Did not attach to PLL_ADV_INST.
pll_dvi pll_dvi是不是不符合规则啊？还有查看一下是否需要调用PLL。 STM_FPGA 发表于 2012-8-27 14:16 static/image/common/back.gif
pll_dvi pll_dvi是不是不符合规则啊？还有查看一下是否需要调用PLL。
就是调用的IP核pll_adv，按如下设置的啊
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