这个状态机老怪，求大神解
modulecounter256_2(clk,q, reset,clock);
input clock; //system clock;
input reset;
input clk;
output q;
reg count;
reg state;
parameter idle=2'b00, low=2'b01, high=2'b11;
initial
begin
count = 8'd0;
state = idle;
end
assign q = count;
always @(posedge clock )
begin
if(!reset)
begin
count <= 8'd0;
state <= idle;
end
else
begin
case(state)
idle:
if(!clk)begin
//count<= 8'd0; //statemachine goes wrong when it exists;
state <= low;
end
else
begin
//count<= 8'd0; //statemachine goes wrong when it exists;
state <= idle;
end
low:
if(clk)begin
count <= count + 8'd1;
state <= high;
end
else
begin
count <= count;
state <= low;
end
high:
if(!clk)begin
count <= count;
state <= low;
end
else
begin
count <= count;
state <=high;
end
default:
begin
count <=count;
state <= state;
end
endcase
end
end
endmodule
用来实现0：255的计数
中间注释两行不去掉时count频繁清零
两个不同的状态机的生成的原理图pdf 附件 里
求解 这种状态机谁写的？拉出去斩了！这也叫状态机？这叫死鸡。
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