Modelsim 怎么仿真减法?
我用Modelsim SE 仿真到 cnt := cnt + direction;出现错误------direction=-1时出错.=1时没问题.这是哪出问题了?-- Quartus II VHDL Template
-- Binary Up/Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity binary_up_down_counter is
port
(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
updown : in std_logic;
q : out integer range 0 to 255
);
end entity;
architecture rtl of binary_up_down_counter is
signal direction : integer;
begin
process (updown)
begin
-- Determine the increment/decrement of the counter
if (updown = '1') then
direction <= 1;
else
direction <= -1;
end if;
end process;
process (clk)
variable cnt : integer range 0 to 255;
begin
-- Synchronously update counter
if (rising_edge(clk)) then
if reset = '1' then
-- Reset the counter to 0
cnt := 0;
elsif enable = '1' then
-- Increment/decrement the counter
cnt := cnt + direction;
end if;
end if;
-- Output the current count
q <= cnt;
end process;
end rtl;
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